Impedance Control PCB Tolerance: ±10% vs ±5% Explained

Impedance tolerance is a manufacturing clause, not just a design note

Every high-speed board drawing carries a line like "50Ω single-ended, 100Ω differential" followed by a tolerance. On the design side, ±10% versus ±5% looks like a one-digit change. On the manufacturing floor it is two different ways of running the job, and in procurement it is two different quote and lead-time structures.

Here is why. Impedance is not a dimension you can machine. No tool cuts 50Ω. It is the calculated result of four physical quantities acting together: trace width, dielectric thickness, copper thickness, and dielectric constant. A fabricator directly controls the first three. The fourth comes from the laminate supplier. So "impedance ±5%" is really a request to tighten four tolerances at once, one of which the factory cannot fully govern.

Sunking PCB's published capability for impedance control PCB reads: impedance tolerance ±5% with ±10% as standard, TDR (time-domain reflectometry) as the test method, impedance range 25Ω–120Ω, differential impedance 85Ω–100Ω, dielectric thickness control ±10%, operating frequency DC–40GHz. In our internal capability register, ±10% is logged as a standard capability and ±5% as an advanced, conditional one. Conditional means it is not automatically available for every stackup, trace width, and board thickness combination; engineering review has to confirm the specific stackup lands in an achievable window. That distinction is what this article unpacks.

What ±10% covers, and what ±5% requires

The short version: most high-speed digital interfaces are fine at ±10%, and staying at ±10% buys you wider stackup choices, more common materials, and shorter engineering confirmation cycles.

The scenarios where ±10% works line up with the applications listed on our impedance control page: DDR memory modules, USB and HDMI interfaces, high-speed backplanes, and standard channels in optical communication modules. These interfaces are designed with tolerance built in. Receivers equalize, and link budgets already reserve margin for interconnect. A 50Ω line landing anywhere between 45Ω and 55Ω will not close the eye.

The cases that genuinely need ±5% are narrower: high-speed channels whose budget is already consumed by trace length, connectors, and vias; RF paths with a specified return loss target; multilayer boards requiring tight impedance consistency across same-name nets on different layers; and projects where the customer's own test specification states ±5% outright. Boards in this group are usually also high-frequency builds, running on materials in the Dk 2.2–10.2 and Df 0.0009–0.003 range documented on our high frequency PCB page.

For tight tolerance to be realistic, several conditions have to hold at once:

1. Dielectric thickness sits in a controllable window. Our dielectric thickness control figure is ±10%. The thinner the dielectric, the more that same ±10% swings the resulting impedance. Very thin dielectric plus tight tolerance can be geometrically unachievable.
2. Trace width is not too fine. Trace width tolerance is ±20% (see tolerance standards). On a 4mil trace that is ±0.8mil; on an 8mil trace it is ±1.6mil, yet the relative impact is smaller. The absolute number is not the risk indicator — the ratio is.
3. Laminate Dk is batch-consistent. Dk is guaranteed by the material supplier. A fabricator can select a more stable grade but cannot correct Dk on the line.
4. The stackup gives way to impedance. This is the most commonly underestimated condition, covered separately below.

If any one of these fails, ±5% should be pushed back during engineering review rather than released to production and then discovered at the TDR step across a full lot.

The four variables behind measured impedance, and their own tolerances

Treating impedance as a deliverable specification lets you decompose its error sources. Ranked by how directly a fabricator controls them:

Trace width — set by imaging and etching. Tolerance ±20%. This is the widest ratio of the four, but also the most compensable: during CAM data preparation the artwork width is adjusted for expected etch loss so the finished trace lands near target. The compensation amount depends on copper thickness and etch method, and it lives in CAM processing rather than on your drawing.

Dielectric thickness — set by lamination. Control figure ±10%. Resin flow, glass style count, and pressure distribution all move the final thickness. This is exactly why impedance-controlled stackups cannot casually swap in an "equivalent" material: two 4mil-nominal dielectrics with different construction do not compress identically.

Copper thickness — set by base foil plus plating. It affects both cross-sectional area and etched sidewall profile. Heavy copper and tight impedance tolerance are natural opponents: thicker copper means more sidewall taper and a less predictable effective width.

Dielectric constant (Dk) — set by the material, not controllable in-house. The Dk range for high-frequency laminates is 2.2–10.2 per our high frequency page. Any grade has an allowed batch-to-batch Dk variation, and that error flows straight into the impedance result.

This decomposition has practical value. When TDR results drift from target, you can work backward by variable. A whole lot reading high with measured trace width narrow points to insufficient etch compensation. Impedance low with trace width nominal usually points to thin dielectric. That analysis is cheapest at first-article confirmation, before volume release.

Test coupons: impedance is measured, not calculated

You cannot probe impedance on the functional traces of a finished board. Probes will not land reliably on fine lines, and the contact itself introduces a discontinuity. The industry answer is a test coupon on the panel border: a length of line on the same layer, at the same width, with the same dielectric structure as the controlled net, with probe-accessible pads at both ends. It travels through every process step with the board, and TDR measures its characteristic impedance as the representative value for that layer.

For a coupon to actually represent your board, a few things need to be explicit in the drawing or engineering notes:

• Which nets are controlled. Not every trace needs impedance control. List the controlled nets or layers and each target value, stating single-ended or differential and the ohm figure. Our covered range is 25Ω–120Ω single-ended and 85Ω–100Ω differential.
• Target and tolerance written separately. Write "50Ω ±10%", not "45–55Ω". The first reads as target plus allowance. The second invites treating any value in the band as equally acceptable.
• Coupon-to-layer correspondence. Different layers on a multilayer board need separate verification. One coupon cannot stand in for all of them.
• Whether a report ships with the order. Whether the TDR report is a deliverable, and whether it is required per lot, is a procurement clause rather than a design one. Raise it when you request a quote.

Coupons consume panel border area and slightly reduce utilization. That is part of the cost of tight tolerance, and it is normally far cheaper than the scrap risk it prevents.

How tight tolerance constrains your stackup

This is the most underestimated cost of ±5%: it limits your stackup freedom in reverse.

The common design flow is to fix layer count and layer order first, calculate impedance second, then adjust trace width if the numbers miss. Tighten the tolerance to ±5% and that adjustment space shrinks until some layer orders have no solution at all. If a signal layer's dielectric to its reference plane has already been squeezed thin by overall board thickness and the other layers' needs, no trace width will save it: a ±10% swing on a thin dielectric already exceeds a 5% impedance budget.

The stackup then has to give way, and the knock-on changes typically include:

• More layers, to get a workable dielectric distribution. Our layer count capability is 40 layers standard and 64 layers maximum (advanced tier, subject to engineering review); see multilayer PCB.
• A different dielectric thickness combination, which often means a different laminate grade. See material options.
• A revised overall board thickness. Board thickness tolerance is ±10% or ±0.005" (whichever is greater), across an available range of 0.2–6.0 mm. Change total thickness and the mechanical assembly interface needs rechecking too.

So the correct sequence is to settle impedance requirements and stackup together, not stackup first and impedance afterward. Handing target impedance, tolerance class, and the controlled net list to your fabricator at the quoting stage costs one engineering cycle less than reworking the stackup after release.

The release evidence chain: TDR report + 100% electrical test + FQC

Pass/fail on an impedance-controlled board is not a single test result. It is three layers of evidence stacked up.

Layer one: TDR time-domain reflectometry. Measures the coupon and reports actual characteristic impedance for the controlled nets, judged against target plus tolerance. This is the direct verdict on whether impedance is in spec, and it is the source of the TDR report.

Layer two: 100% electrical test. Flying probe or fixture, applied to every order. It checks continuity and shorts, not impedance. The two solve different problems: TDR says whether the impedance is right, electrical test says whether the connections are right. Neither substitutes for the other.

Layer three: FQC and in-process gates. The process carries 10+ inspection gates, with final inspection before shipment covering appearance, dimensions, hole position, and solder mask registration. Solder mask registration tolerance is ±0.003" and hole position ±0.003". The overall published figures are a 99.8% pass rate and under 0.3% scrap. Full detail on the inspection system is on our quality control page.

What procurement needs to confirm is which of these three layers arrive as documents. The TDR report usually has to be requested explicitly at quoting time — it is not a default deliverable. Retention and traceability of inspection records fall under the quality system.

When you should not write ±5%

Writing a tight tolerance costs nothing. Delivering it does. In these situations ±5% is pure waste:

• The interface protocol is already tolerant. Standard USB 2.0, low-speed SPI, I2C and similar nets do not need impedance control at all, so the callout does nothing.
• "Just to be safe." Tightening tolerance without simulation or a link budget to justify it eliminates workable stackup options and, on balance, raises risk.
• The stackup is already locked by other constraints. If thickness, layer count, and mechanical interface are all fixed, tight tolerance may have no solution and engineering review will send it back.
• You do not intend to verify it. Requiring ±5% while declining the TDR report and skipping first-article confirmation makes the number unenforceable.
• Single-layer, single-net low-speed boards. The control complexity and the benefit are mismatched.

The reverse error is worse. Skipping tight tolerance where it was needed surfaces during bring-up: the board exists, the eye fails, and now you are separating interconnect problems from design problems. That costs more than stating the requirement clearly up front. The deciding input should be your link budget, not habit.

FAQ

Q1: How much more does ±5% cost than ±10%?

The difference does not come from the tolerance number itself. It comes from what the number triggers: whether the stackup needs redesign, whether a different laminate grade is required, whether layer count increases, whether a TDR report is issued, and how much panel border the coupons consume. Pricing follows from those answers. Sending target impedance, tolerance, controlled nets, and report requirements together gets you a far more accurate quote than "impedance control required."

Q2: Does the TDR report ship by default?

No. TDR is the test method for impedance-controlled boards and the measurement is an in-process step, but whether the report ships with the order and whether it is provided per lot is a procurement clause that needs to be stated in the RFQ or purchase order. 100% electrical test, by contrast, covers every order as standard.

Q3: Why can't impedance be measured directly on the finished traces?

Probes cannot make reliable contact with fine traces, and the contact itself introduces an impedance discontinuity, so the reading would not represent the actual channel. A test coupon shares the layer, trace width, dielectric construction, and full process history with the controlled nets, which is why using it as the representative measurement is standard industry practice.

Q4: My board is a high-frequency build. Do I use the ±5% on the high frequency page or the ±10% standard on the impedance page?

Both pages describe the same capability. ±10% is standard; ±5% is an advanced, conditional tier requiring engineering review to confirm the specific stackup can deliver it. Whether the board is a high-frequency build does not change that logic — it changes the usable material range and the loss requirements. Dk and Df ranges for high-frequency laminates are on the high frequency page.

Q5: If I change the tolerance requirement, does the stackup have to be redone?

Going from ±10% to ±5% usually requires recalculation, because a ±10% dielectric thickness control figure may already consume most of the impedance budget. Relaxing from ±5% to ±10% does not normally require a redo, but stackup accommodations already made for tight tolerance — extra layers, for instance — can be simplified. That is a cost-reduction opportunity worth checking.

Q6: Can an out-of-spec impedance board be reworked?

No. Impedance is set by trace width, dielectric thickness, copper thickness, and Dk, and all four are locked once lamination and etching are complete. No downstream process changes them. That is precisely why first-article confirmation and engineering review matter: impedance problems can only be prevented before release, not repaired afterward.