IC Substrates & Substrate-like PCB (SLP)
We own the engineering, DFM review and qualification of your IC substrate, and deliver it through dedicated substrate lines and specialist substrate fabs. Down to 10/10 µm line/space, φ40 µm laser vias and 20+ build-up layers.
IC substrate, SLP and HDI — where the lines are drawn
IC substrate vs. HDI PCB vs. standard PCB
| Parameter | IC substrate | HDI PCB | Standard PCB |
|---|---|---|---|
| Min line / space | 10/10 µm (ABF) to 25/25 µm (SLP) | 50/50 to 75/75 µm | 100/100 µm and above |
| Via formation | UV / CO₂ laser blind vias, φ40–60 µm, via-fill plated and stackable | CO₂ laser blind vias, φ75–100 µm, limited stacking | Mechanical drilling from φ0.15 mm, mostly through-holes |
| Base material | ABF build-up film, BT resin, low-CTE cores | High-Tg FR4, modified epoxy, some PPE / hydrocarbon systems | Conventional FR4 (Tg 130–150 °C) |
| Typical application | FC-BGA, FC-CSP, memory and RF packages, chiplet carriers | Smartphone mainboards, wearables, module boards | Industrial control, power supplies, appliances, automotive body electronics |
| Dimensional tolerance / warpage | ±15 µm registration, warpage ≤0.5% measured post-reflow | ±50 µm registration, warpage ≤0.75% | ±100 µm registration, warpage ≤1.0% per common IPC-6012 practice |
The substrate window and the bare-board window on our /capabilities page (4/4 mil class) belong to different lines and different qualification regimes; neither figure can be read across to the other.
Substrate types
Six types by package format and interconnect.
ABF build-up
Highest fine-line capability
| Parameter | Capability |
|---|---|
| Min. line/space | 10 / 10 µm |
| Laser via diameter | φ40 µm |
| Build-up layers | ≥ 20 layers |
| Max. body size | 100 mm square class |
| Pattern formation | Full SAP |
| Core structure | Cored / coreless |
| Typical package | FC-BGA, chiplet |
| Dielectric | Ajinomoto Build-up Film |
- Features
- Layer-by-layer, laser vias
- Dense fan-out
- Film and capacity scarce
- Applications
- CPU / GPUAI acceleratorServerSwitch ASIC
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
BT resin
Memory and mid-I/O workhorse
| Parameter | Capability |
|---|---|
| Min. line/space | 15 / 15 µm |
| Line capability band | 15–25 µm |
| Build-up | 4 + 4 |
| Tg | ≥ 190 °C |
| CTE (x/y) | approx. 12 ppm/K |
| Core material | BT resin |
| Typical package | FC-CSP, MCP |
| Moisture uptake | Low |
- Features
- Stiff, dimensionally stable
- Lower cost than ABF
- Warpage easier to hold
- Applications
- MemoryRF moduleMCPConsumer
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
Flip-chip (FC)
Bump-attached, high I/O
| Parameter | Capability |
|---|---|
| Bump pitch | from 130 µm |
| Micro-bump pitch | down to 40 µm |
| Substrate line/space | 10–15 µm |
| Warpage | ≤ 0.5 % |
| Package form | FC-CSP / FC-BGA |
| Substrate system | ABF / BT |
- Features
- All bumps must contact
- Reflow warpage critical
- Pad coplanarity held
- Applications
- ProcessorBasebandGPUHigh-speed I/O
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
Wire-bond (WB)
Wire-connected, cost-controlled
| Parameter | Capability |
|---|---|
| Bond finger pitch | from 50 µm |
| Substrate line/space | 20 / 20 µm |
| Layer count | 2–8 layers |
| Surface finish | ENEPIG / soft gold |
| Package form | WB-CSP / WB-BGA |
| Substrate system | Mainly BT |
- Features
- Finger plating bondability
- Mature structure
- Suits mid/low I/O
- Applications
- MCUSensorPMICFingerprint
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
SLP
Substrate-like main board
| Parameter | Capability |
|---|---|
| Min. line/space | 25 / 25 µm |
| Pattern formation | mSAP |
| Laser via diameter | φ60 µm |
| Interconnect | Any-layer (ELIC) |
| Finished thickness | 0.6–1.0 mm |
- Features
- Board built substrate-style
- Higher component density
- Frees product space
- Applications
- Phone main boardWearableTabletTWS
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
MIS
Plated circuit, moulded, ultra-thin
| Parameter | Capability |
|---|---|
| Circuit structure | Single/double plated layer |
| Min. line/space | 30 / 30 µm |
| Finished thickness | 0.1–0.2 mm |
| Stepped pad | Optional |
- Features
- Moulded, no laminate
- Thinner than build-up
- Suits small bodies
- Applications
- FingerprintCamera moduleSensorLED
Specs are confirmed per project; substrates are built on dedicated substrate lines and partner substrate fabs.
Core process capabilities
Volume window and limit capability for IC substrates and SLP only.
Circuit imaging
| Parameter | Standard window | Advanced |
|---|---|---|
| Min line / space (SLP, mSAP) | 25/25 µm | 20/20 µm |
| Min line / space (ABF, SAP) | 15/15 µm | 10/10 µm |
| Min pad pitch (bump pitch) | 80 µm | 40 µm |
| Finished copper thickness (build-up layers) | 12–15 µm | 8–10 µm (fine-line builds) |
The fine-line window depends on the specific stack-up, copper thickness and panel size, and is confirmed per build together with the substrate line.
Vias & build-up structure
| Parameter | Standard window | Advanced |
|---|---|---|
| Laser via diameter | φ60 µm | φ40 µm |
| IC substrate layer count | 4–14 layers | 16–64 layers |
| Build-up stages per side | 2–4 stages | 5–6 stages, coreless options available |
| Dielectric layer thickness (ABF) | 25–40 µm | 15–25 µm |
| Microvia aspect ratio (depth : diameter) | 0.6 : 1 | 0.8 : 1 (stacked vias) |
Dimensional accuracy & warpage
| Parameter | Standard window | Advanced |
|---|---|---|
| Layer-to-layer registration | ±15 µm | ±10 µm |
| Warpage (room temperature, ratio over diagonal length) | ≤0.7% | ≤0.5% |
| Profile tolerance (routing / laser singulation) | ±50 µm | ±25 µm |
| Finished thickness tolerance | ±10% | ±8% |
Warpage is the maximum measured deviation divided by the substrate diagonal at room temperature. High-temperature (reflow-profile) warpage data is agreed separately during engineering review.
Surface finish & electrical performance
| Parameter | Standard window | Advanced |
|---|---|---|
| Surface finish options | ENIG, OSP | ENEPIG, electrolytic Ni/Au, solder bump / SOP pads |
| Solder-mask opening tolerance | ±15 µm | ±10 µm |
| Min solder-mask dam width | 50 µm | 35 µm |
| Impedance control | ±10% | ±5% |
| Electrical test | 100% flying-probe open / short test | High-speed fixture test, optional insulation-resistance and high-frequency characterisation |
Material library
Material systems used in IC substrates
| Material | Type | Dk / Df | Tg | Typical use |
|---|---|---|---|---|
| Ajinomoto ABF (GX / GZ series) | Glass-free build-up film, laminated layer by layer, laser-drilled and patterned by SAP plating | approx. 3.1–3.3 / approx. 0.010–0.016 (10 GHz) | approx. 155–175 °C | FC-BGA, CPU / GPU / ASIC carriers, chiplet fan-out |
| Mitsubishi Gas Chemical BT (HL832 class) | Glass-reinforced BT resin cores and prepreg, workable either subtractively or by mSAP | approx. 3.6–3.8 / approx. 0.007–0.010 (10 GHz) | approx. 190–270 °C depending on grade | Memory packages, MCP, FC-CSP, RF module carriers |
| Panasonic (build-up / low-loss grade) | Low-loss resin build-up cores and prepreg on thin glass reinforcement | approx. 3.3–3.5 / approx. 0.004–0.006 (10 GHz) | approx. 195–215 °C | SLP boards, high-speed module boards, build-up structures with a loss budget |
| Shengyi (high-speed / high-frequency grade) | Modified-resin cores for high-speed digital and high-frequency use, with a more controllable domestic supply chain | approx. 3.3–3.7 / approx. 0.003–0.006 (10 GHz) | approx. 200–220 °C | High-speed SerDes modules, RF front-end carriers, domestic-substitution builds |
| Hitachi (build-up grade) | Build-up cores and prepreg aimed at low CTE and dimensional stability | approx. 3.7–4.0 / approx. 0.008–0.012 (10 GHz) | approx. 185–210 °C | Wire-bond BGA / CSP, automotive-grade packages, warpage-sensitive build-up structures |
Vendor datasheet ranges are representative, not grade guarantees; Dk/Df and Tg vary with test frequency, method and grade, with actual values confirmed with the substrate fab at stack-up freeze.
Technology roadmap
Two parallel tracks: process sets fineness, package format sets interconnect load.
Patterning process
Subtractive etching
Practical floor around 50/50 µm; finer than that, yield and impedance consistency degrade together
mSAP (modified semi-additive process)
25/25 µm in volume production and compatible with any-layer interconnect; limited by flash-etch uniformity on the thin foil, it generally tops out near 15 µm
SAP (semi-additive process)
10/10 µm in volume with 20+ build-up layers and stacked vias — the only realistic route for FC-BGA and chiplet carriers
Package format
Wire bonding
Substrate requirement: bond-finger pitch ≥50 µm, ENEPIG / soft-gold finish, local flatness in the bonding area matters more than whole-panel warpage
Flip-chip
Substrate requirement: 10–15 µm L/S, 130 µm bump pitch (40 µm micro-bump), ±15 µm registration, ≤0.5% post-reflow warpage
2.5D / fan-out interposer
Substrate requirement: 100 mm square class bodies, 20+ build-up layers, thousands of BGA balls, with whole-panel warpage and copper balance simulated during stack-up design
Applications
Different applications load different parameters.
Memory packages (DRAM / NAND)
- Detail
- Typical substrate: BT build-up substrate, 2+2 or 4+4, 20–25 µm L/S
- Additional
- Governing constraint: warpage on an ultra-thin core — reflow warpage on a 0.13 mm class substrate must stay inside 0.5% of the diagonal
RF front-end modules
- Detail
- Typical substrate: low-loss BT or modified ABF carrier, 4–8 layers, with cavities and shielding via walls
- Additional
- Governing constraint: insertion loss and Dk consistency — Df ≤ 0.005 at 10 GHz with within-lot Dk spread held to ±2%
AI and HPC processors
- Detail
- Typical substrate: ABF build-up substrate, 10+10 build-up and beyond, 10/10 µm L/S, FC-BGA format
- Additional
- Governing constraint: warpage and bump coplanarity at large body size — the coplanarity and reflow-warpage window must still hold across a 100 mm square body
MEMS sensors
- Detail
- Typical substrate: cavity BT substrate or ceramic carrier, 2–6 layers, with acoustic / pressure openings
- Additional
- Governing constraint: low stress and cavity geometry — ±15 µm cavity depth tolerance, controlled cavity-floor flatness and minimised package residual stress
Automotive radar
- Detail
- Typical substrate: millimetre-wave low-loss carrier (modified PPE / hydrocarbon system), 4–8 layers, with an integrated antenna layer
- Additional
- Governing constraint: millimetre-wave line geometry — ±5 µm antenna line-width tolerance, ±5% dielectric thickness tolerance, validated through automotive temperature cycling
Power modules
- Detail
- Typical substrate: heavy-copper or embedded-coin carrier, insulated metal substrate (IMS) or ceramic substrate, 2–6 layers
- Additional
- Governing constraint: thermal-path resistance — junction-to-case thermal resistance minimised with 70–210 µm copper, matched to the power-cycling life requirement
Process flow
Nine steps with build-up repeated per designed layer; we run engineering review, with fabrication on dedicated substrate lines.
01 Core preparation or coreless carrier
Through-holes drilled and plated in the core, or a coreless carrier started. Sets rigidity and total thickness.
02 Laser via formation
Blind vias opened layer by layer with UV or CO₂ laser, from φ40 µm, with copper exposed at the via bottom.
03 Desmear and electroless seed layer
Plasma or chemical desmear, then an electroless copper seed layer of 5–8 µm.
04 Pattern plating (mSAP / SAP)
Dry film imaging followed by pattern plating; this step sets the fine-line accuracy.
05 Resist strip and flash etch
Resist stripped and the seed layer flash-etched away; etch uniformity decides line-width consistency.
06 Build-up dielectric lamination
ABF or prepreg vacuum-laminated over the conductors under heat and pressure.
07 Repeat build-up cycles
Steps 02–06 repeat for the designed layer count; accumulated registration error narrows the window each cycle.
08 Solder resist and surface finish
Photoimageable solder resist opened over the pads, then ENEPIG or OSP according to the assembly method.
09 Singulation and final inspection
After singulation, final inspection covers appearance, electrical test, coplanarity and warpage.
Quality & reliability
Qualification follows the agreed test plan, with seven common tests listed below.
High Temperature Storage (HTS)
- Detail
- Typical condition: 150 °C, 1000 h
- Additional
- Failure usually points to over-cured brittle resin, excessive intermetallic growth in the surface finish, or loss of adhesion at the copper/resin interface.
Temperature Humidity Bias (THB)
- Detail
- Typical condition: 85 °C / 85 % RH, 1000 h under bias
- Additional
- A drop in insulation resistance or CAF filament growth means the spacing, glass-weave treatment or the moisture resistance of the build-up and solder-mask materials has to be re-engineered.
Thermal Cycling Test (TCT)
- Detail
- Typical condition: −55 °C to +125 °C, 1000 cycles
- Additional
- Via-bottom cracking or interlayer delamination indicates the aspect ratio, target-pad design or the CTE pairing of the materials needs to change.
Reflow Resistance & MSL Classification
- Detail
- Typical condition: MSL 3, 260 °C peak, 3× reflow
- Additional
- Delamination or out-of-spec warpage means a stricter dry-pack level, a lower-moisture build-up material, or a more symmetric stack-up is required.
Solder-Ball Shear Test
- Detail
- Typical condition: measured as-reflowed and after 150 °C ageing or multiple reflows for comparison
- Additional
- A brittle interfacial fracture, rather than a ductile break inside the ball, points to an over-thick intermetallic layer or contamination in the surface finish.
C-SAM Acoustic Imaging
- Detail
- Typical condition: scanned before and after reliability stress and compared as a delta
- Additional
- Delamination signatures that appear only after stress are direct evidence that the stack-up design or lamination parameters need correcting.
Cross-Section Analysis
- Detail
- Typical condition: sampled per lot, plus failure localisation on every reliability reject
- Additional
- The section is what assigns a problem to its owner: thin via-wall copper is process capability, a thin dielectric is material and lamination, and misregistration is imaging and scaling compensation.
Accepted to both IPC-6012 Class 3 and IPC-6016. The acceptance class, sampling plan and test plan are agreed before the order is placed.
Frequently asked questions
What is the minimum order quantity for IC substrates?
IC substrates are ordered by the panel, not by the individual unit, and engineering samples typically start at 2–5 panels. Send the substrate outline and the quotation will include the panelisation drawing and the units-per-panel count.
Which design file formats do you accept for IC substrates?
We accept Gerber (RS-274X), ODB++ and IPC-2581, and prefer ODB++ or IPC-2581 because they carry the netlist and stack-up. A stack-up drawing, the impedance requirements and the substrate outline are needed alongside the artwork.
How is confidentiality handled? Can an NDA be signed first?
An NDA can be signed before any data is exchanged; we accept your version or provide a standard mutual agreement. For a pre-NDA estimate, the layer count and the line/space class are enough.
What qualification and first-article flow should we expect?
Four stages: a DFM review that locks the stack-up and impedance model, first-article inspection on engineering samples, reliability testing on a qualification lot, then production release. The test items follow the plan agreed with you.
What information is needed to quote an IC substrate?
Four items decide the quotation: substrate type (FC-BGA, WB-BGA, SLP and so on), total layer count with the build-up structure, the finest line/space class, and the substrate outline. The rest is filled in at DFM review.
Who actually fabricates the substrates? Are they built in-house?
Fabrication takes place on dedicated substrate lines and at specialist substrate fabs, not on a general printed-board line. We own the engineering: stack-up and impedance design, DFM review, qualification management and delivery.
Engineering focus
- Confirm substrate (incl. BT) and finish (incl. wire-bond related interfaces) per application
- Review fine-line and microvia windows against the order structure — no stacked extremes
- Capture size, gold thickness and test requirements in acceptance — no verbal defaults
Inspection & traceability
- Inner & outer layer 100% AOI
- Flying probe for prototypes; fixture test for volume
- ENIG nickel/gold thickness via XRF
- Impedance boards verified with TDR coupons
- Multilayer X-ray registration; microsection sampling for stack-up
- Delivery yield 99.8%; scrap controlled below 0.3%
Project inputs & review
- Application type (COB/module/substrate-like) and material requirements
- Stack-up, trace/via structure and finish (incl. gold thickness)
- Sample/trial/volume stage and acceptance criteria
Start an IC substrate project
Send your stack-up requirements, package format and volume. We run the DFM review first, then come back with a proposal and quotation.