4, 6 or 8 Layers? Multilayer PCB Layer Count Compared

Layer count is not a routing-density question

"We ran out of room, add two layers" is the most common way layer count gets decided, and the most common reason a board gets re-spun. What actually sets layer count is not whether the traces fit. It is how many complete reference planes the board needs.

Here is why. A high-speed signal's return current travels in the plane immediately adjacent to it. If that plane is split, cut by routing, or simply absent, the return has to detour. Impedance goes out of control and common-mode noise rises. This happens on boards that route to 100% completion, because it has nothing to do with whether the traces fit.

So the correct question set is: for every high-speed routing layer, is the adjacent layer a solid plane? How many independent voltage domains does the power section need, and does each need its own plane? What impedance targets and what tolerance band? Answer those and the layer count is largely decided. What remains is checking it against manufacturing limits.

Stackup structure fundamentals — cores, prepreg, symmetry, layer ordering — are covered separately in the multilayer PCB stackup design guide. This article does one thing: compare 4, 6 and 8 layers as a trade-off, and state the ceiling and the cost of each.

The deployed multilayer PCB page specifies layer count 4–64 (40 in volume production, 64 maximum), board thickness 0.4–6.0 mm, minimum trace/space 3/3 mil, minimum hole 0.1 mm, and impedance ±5% (±10% standard). Every judgement below stays inside that envelope.

4 layers: where it works and where it starts costing you

The typical 4-layer order is signal — ground — power — signal. The first thing it buys is one solid ground plane, and that alone covers a large share of mid-speed digital and mixed-signal boards.

What 4 layers can do:

• give top-layer routing an adjacent solid ground plane for return current;
• distribute a single main voltage domain with adequate decoupling;
• support controlled-impedance single-ended traces, provided those traces stay on the layer adjacent to the ground plane;
• reach thin finished thicknesses, down to the 0.4 mm end of the range.

What 4 layers cannot do without paying for it:

• The reference plane for bottom-layer routing is the power plane. If that plane is split across several voltage domains, bottom-side high-speed traces cross the splits and the return path breaks. This is the most common hidden defect in 4-layer designs.
• Both routing layers are external. Outer-layer impedance is more exposed to etch and solder-mask variation than inner-layer impedance, so tight impedance targets are harder to hold there.
• With multiple voltage domains, the more the power plane is carved up, the less usable reference area remains. You are trading plane integrity for domain count.

Short rule: one main voltage domain plus high-speed routing that can stay on the top layer — 4 layers is usually enough. Add voltage domains, or force high-speed routing onto both faces, and 4 layers starts accumulating debt.

6 layers: two distinct allocations, and picking wrong wastes the upgrade

Six layers is where the trade-off is densest, because there are two genuinely different ways to use it and they buy different things.

Allocation A: signal — ground — signal — signal — power — signal (4 routing layers, 2 planes)

• Buys routing layers. Suits high pin-density boards with heavy routing volume but moderate edge rates.
• Cost: the two inner signal layers sit adjacent to each other, raising layer-to-layer crosstalk risk, and each has a plane on one side only.

Allocation B: signal — ground — signal — power — ground — signal (4 routing layers with a second plane pair)

• Buys reference-plane quality. Critical routing layers can be sandwiched between planes, so return paths stay short and deterministic.
• Cost: the layers genuinely free for unconstrained routing shrink, so floorplanning has to happen earlier.

The deciding factor is not layer count. It is whether this board is short on routing space or short on return-path quality. Short on space, take A. Short on return quality, take B. Building a board that needs B on an A stackup means paying for six layers and getting four layers of electrical performance — the most expensive mistake in layer-count planning.

Six layers brings a second practical gain: at least one signal layer can move inward, where impedance consistency beats outer layers. If the project carries a ±5% impedance requirement (see impedance control PCB: 25–120Ω range, 85–100Ω differential, dielectric thickness controlled to ±10%, TDR tested), putting the critical nets on an inner layer is the safer route.

8 layers and up: symmetric plane pairs and impedance headroom

At eight layers the arrangement finally gets comfortable. A representative order is signal — ground — signal — power — ground — signal — ground — signal, and the defining feature is that several signal layers can be sandwiched between planes while the stackup stays symmetric top to bottom.

Eight layers buys four things:

1. Plane pairs. High-speed layers have a reference surface above and below, giving the shortest return path and the lowest common-mode radiation.
2. Independent power planes. Multiple voltage domains each get a plane, or power and ground sit adjacent to form plane capacitance that improves power integrity.
3. Impedance headroom. More dielectric thickness combinations are available, so there is more room to land trace width, dielectric thickness and target impedance inside the ±5% band. Dielectric thickness itself is controlled to ±10%; more layers means more combinations to tune.
4. Symmetry. A symmetric stackup warps less after lamination, which directly affects assembly yield at SMT.

The costs are also four, and all of them need checking early:

• Thickness rises. More dielectric and copper layers put the finished board toward the thicker end. The product page range is 0.4–6.0 mm; the actual value has to be set together with the thickness target and impedance scheme, subject to engineering review. The cover diagram shows one 8-layer arrangement with 35/140/200/255 µm callouts — note the "Only nominal values" note along its edge. Those are illustrative nominal figures, not a capability commitment.
• Aspect ratio. A thicker board raises the aspect ratio for any given hole diameter. The capabilities page states a maximum aspect ratio of 10:1. Board thickness divided by minimum hole diameter has to stay inside that ratio, or the hole grows or the board gets thinner.
• Minimum hole is bounded by thickness. The product page lists a 0.1 mm minimum hole, but that is a capability ceiling. The smallest usable hole must be computed against actual board thickness via aspect ratio; 0.1 mm cannot simply be applied to any thickness.
• Tier transitions. Up to 40 layers sits in the Standard tier; above 40 moves into Advanced/R&D. Eight layers is well inside Standard, but requiring sub-3 mil traces or sub-0.15 mm mechanical drilling at the same time can push the whole board into a higher tier. Layer count and process tier are two separate axes — do not conflate them.

The real cost of adding layers: three numbers that move together

The most frequently missed point in layer-count planning is that board thickness, aspect ratio and minimum hole diameter are coupled. You cannot read them off separate spec rows independently.

• Board thickness 0.4–6.0 mm (product page) / 0.2–6.0 mm (capabilities page, including thinner low-layer-count boards);
• maximum aspect ratio 10:1;
• minimum mechanical drill 0.15 mm, minimum hole 0.1 mm (laser drilling reaches 0.075 mm, but that is HDI microvia processing).

The arithmetic is direct: board thickness ÷ minimum hole diameter ≤ 10. An 8-layer board toward the thicker end has its smallest usable hole lifted by that inequality. Conversely, if the design demands very small through holes, thickness has to come down, dielectrics get thinner, and the impedance scheme needs recalculating. All three have to hold at once.

Hole and position tolerances are specified separately: hole diameter ±0.05 mm, positional accuracy ±0.025 mm, backdrill control ±0.05 mm. The full tolerance table is on the tolerance page. On the copper side, inner-layer copper weight selection and its mutual constraint with trace width is covered in PCB copper thickness options and design rules, so it is not repeated here.

Material trade-offs (FR-4 versus high-frequency or high-Tg systems) are on the materials page. One point matters here: change the dielectric system and the thickness combinations and impedance scheme for the same layer count all have to be recalculated. Copying the layer table across is not sufficient.

The dividing line: when adding layers will not help

There is one situation extra layers cannot fix: a trapped BGA fanout. When pitch gets tight enough that conventional through holes will not fit between pads, the constraint is hole and pad geometry, not layer count. Adding layers only thickens the board and worsens aspect ratio while the fanout stays blocked.

Three signals to watch for:

1. Fine-pitch BGA pins need to reach inward through several layers, and conventional vias consume more inter-pad space than is available;
2. minimum hole diameter is already pinned by aspect ratio, and going thicker forces a larger hole that no longer fits the pad array;
3. via-in-pad or any-layer interconnect is needed to free up routing space.

When those appear, the correct move is a buildup structure. HDI PCB specifies layer count 4–20, 2/2 mil trace/space, 0.075 mm laser vias, ±25 μm layer-to-layer registration, 1+N+1 through 5+N+5 buildups, and FR-4/BT/ABF substrates. The capabilities page adds that 1+N+1 through 5+N+5 are available in Standard, Advanced and R&D tiers, while Any Layer is offered in Advanced and R&D only.

Put plainly: layers buy planes and routing space; microvias buy fanout capability. They are not substitutes. Short on planes, add layers. Short on fanout paths, go HDI. A board short on both needs both, and at that point the stackup gets designed from scratch rather than by appending two layers to the existing order.

Freeze this list before release

Once layer count enters manufacturing, changing it is expensive: stackup table, impedance scheme, drill table and finished thickness all move together. Freeze the following before release and submit them with the data package:

1. Layer count and the complete layer order: the role of each layer (signal/ground/power), whether planes are split, and where.
2. Target finished thickness and tolerance: state whether it includes solder mask and surface finish.
3. Impedance requirements: single-ended and differential targets, tolerance band (±5% or the ±10% standard), and which nets are controlled.
4. Minimum hole diameter and via types: through, blind/buried, backdrill needs — checked against thickness for the ≤10:1 aspect ratio.
5. Inner and outer copper weights: call out base foil and finished copper separately, not one number.
6. Dielectric material system: grade or specific laminate requirement, and whether engineering-equivalent substitution is permitted.
7. Acceptance class: IPC-A-600 Class 2 or Class 3, and electrical test requirements (100% electrical test is standard).
8. Symmetry requirement: whether a symmetric stackup is mandatory for warpage control.

Anything conditional — thick boards with small holes, above 40 layers, or impedance schemes tightly coupled to thickness — should be marked "subject to engineering review" rather than written as a fixed value. Once the package is complete, submit through the quote request; inspection and acceptance criteria are on the quality page.

FAQ

Q1: Going from 4 to 6 layers, what is the direct gain?

If the two extra layers become a second plane (allocation B), the gain is planes above and below the critical routing layers — deterministic return paths and steadier impedance. If they become two extra routing layers (allocation A), the gain is routing space. You cannot have both, so confirm which one this board is short of before choosing.

Q2: How much better is impedance control at 8 layers than at 6?

The tolerance bands are identical: ±5%, with ±10% standard (product page and capabilities page agree). The difference is not the number but the difficulty of hitting it. Eight layers offers more dielectric thickness and layer-order combinations, so there is more margin to land trace width, dielectric thickness and target impedance inside ±5%. The same tight requirement at six layers may need a narrower window of materials and thicknesses; the specific scheme is subject to engineering review.

Q3: Does adding layers force a larger minimum hole?

Yes, but layer count is not the direct cause — thickness is. Maximum aspect ratio is 10:1, so as thickness rises the ratio for a given hole diameter grows, and beyond 10:1 the hole must grow or the board must get thinner. Layer count, thickness and minimum hole have to be computed together rather than reading the 0.1 mm minimum hole in isolation.

Q4: Does an 8-layer board have to be symmetric?

A symmetric stackup reduces post-lamination warpage risk and is friendlier to downstream SMT assembly, so it is the recommended approach. Whether it is mandatory depends on thickness, copper balance and assembly requirements, which makes it subject to engineering review. If you have a specific warpage limit, state it in the data package.

Q5: When should the design jump to HDI instead of continuing to add layers?

When the bottleneck is fine-pitch BGA fanout rather than reference planes. The signals are: conventional vias no longer fit between pads in the array, minimum hole is already pinned by aspect ratio, and via-in-pad or any-layer interconnect is required. Adding layers there only thickens the board while the fanout stays blocked; move to a 1+N+1 through 5+N+5 buildup instead (Any Layer in Advanced/R&D tiers only).

Q6: With layer count settled, what else must the data package contain to clear review in one pass?

The four most commonly missing items: the complete layer order (role of each layer and plane split locations), the finished thickness datum (whether it includes mask and surface finish), the controlled-impedance net list with tolerance band, and inner/outer copper called out as base foil and finished copper separately. Any one of those missing triggers another round of questions.