Why most drilling defects only surface after plating
Drilling is the most underestimated operation in PCB fabrication. It looks like a machine simply executing a drill file — no chemistry, no lamination parameters. From a quality standpoint, though, drilling is a delayed-detection operation: right after the holes are made, almost nothing looks wrong under optical inspection. The problems appear later, after hole metallisation and plating, sometimes only after thermal stress testing, and they appear wearing a different face.
The reason is that drilling does not really determine whether a hole exists. It determines the physical condition of the hole wall and the positional relationship between the hole and the inner-layer copper. As the drill cuts, it leaves resin smear, protruding glass fibres and micro-cracks on the barrel wall. None of those cause an open circuit by themselves. What they do decide is whether electroless and electroplated copper can adhere uniformly through the full depth of the hole. A hole with uneven adhesion may still read as continuous during E-test, and only reveal barrel separation during thermal cycling. In the Sunking PCB inspection set, thermal stress and solderability testing specifically checks for barrel separation, delamination and plating peel — precisely the class of problem that is seeded during drilling, locked in during plating, and cashed out under thermal stress.
Hole position follows a second delay chain. On a multilayer board, one hole has to register to pads on every relevant inner layer. A drift measured right after drilling reads as a few tens of microns, which does not look serious. It becomes serious when inner-layer copper is breached or the annular ring falls short, and that only shows up in a microsection or as an inter-layer failure in E-test. Inner-layer defects cannot be reworked after lamination — the same logic stated at the inner-layer AOI gate applies to hole position: once a hole is drilled in the wrong place, no downstream process can move it back.
So drilling inspection is not designed as "drill, then take a look." It is designed by splitting the judgement across process points, using at each point a method that can actually see the quantity in question.
The four quantities that are actually judged
Writing "hole size 0.3mm" on a drawing is easy. On the manufacturing side, the judgement on drilling lands on four mutually independent quantities. Their tolerances come from different sources and they need different inspection methods.
One: hole-size tolerance. The Sunking PCB tolerance standard bands this by hole type and size: plated holes (<0.247") ±0.003", non-plated holes (<0.250") ±0.002", larger holes ±0.005". Slots are banded separately: non-plated ±0.005", plated ±0.010". Note that the plated-hole tolerance is wider than the non-plated one. That is not laxity — the finished size of a plated hole is the drilled size minus the barrel plating thickness, so one more variable is in play. When dimensioning holes, state explicitly whether the figure is the finished hole size or the drilled size. Not distinguishing between the two is the single most common ambiguity in RFQ packages.
Two: hole position accuracy. The tolerance is ±0.003" (≈0.076mm), and it is specified together with annular ring and pad size. Hole position is not a standalone metric: the same ±0.003" drift is harmless on a generous pad and immediately rejectable on an annular ring that was only just sufficient. Position must therefore be judged together with the pad design — which is exactly why the tolerance table puts "hole location" and "annular ring / pad size" on the same line.
Three: inner-layer hole-to-copper clearance. This one gets dropped often. The minimum inner-layer hole-to-copper requirement is hole diameter +0.020". It does not constrain the hole; it constrains how much room the inner-layer pattern has to reserve for positional drift and the drill-damage zone. A multilayer design that applies outer-layer clearance rules to inner layers will be flagged back at CAM data review.
Four: hole-wall condition. The first three are dimensions and can be measured. Hole-wall condition is morphology, and can only be observed. It covers wall roughness, resin smear, protruding glass fibres, nail-heading, exit burrs and broken-bit debris. There is no drawing-level numeric tolerance for it; the criteria come from IPC-A-600 Class 2 morphology requirements — Sunking PCB products are inspected to that standard, with the detailed acceptance text governed by the standard itself, not restated here.
Of the four, the first three can be judged right after drilling. The fourth needs magnified observation and destructive microsectioning, and only carries full meaning after plating.
Methods and timing: what each one can see
Mapping methods to process points is what makes it clear why no single inspection method covers drilling quality.
Within the drilling operation: automatic drill-diameter verification plus a dedicated multilayer test coupon. The Sunking PCB drilling gate does two things. The machine verifies drill diameters automatically, which blocks the batch-scale error class of using the wrong bit. Multilayer boards additionally carry a dedicated test coupon to check hole position relative to the inner layers and confirm registration margin. The coupon runs the same process in the same batch as the production panel, so measuring the coupon measures the board — the same logic used at the outer-layer etch gate to verify trace width is used here to verify registration.
After plating: non-destructive copper thickness measurement plus conditional microsection. Five or more points per production panel are measured non-destructively. Heavy copper builds and high-aspect-ratio holes get an additional microsection to confirm hole-wall copper uniformity. The banding logic is worth noting: sampled thickness measurement is sufficient for ordinary holes, but high-aspect-ratio holes require a microsection, because the deeper and finer the hole, the more likely the mid-barrel plating is thinner than at the entry, and non-destructive measurement cannot see mid-barrel.
Microsection analysis: the only complete hole-wall criterion. A microsection examines four things — hole-wall copper thickness, layer registration, the lamination bond line and plating structure. It is destructive, performed on sampled test coupons, so 100% coverage is impossible by definition. Its value is that it is the only method that simultaneously shows what the barrel plating actually looks like and where the hole actually sits relative to the inner layers.
After routing: vision measurement. Outline tolerance, hole-position accuracy and board thickness are measured on a vision measuring system after routing. This is the final confirmation of hole position, because if the routing datum and the drilling datum disagree, a hole can pass right after drilling and fail on the finished board.
E-test: continuity, not hole quality. Flying probe or fixture E-test is confirmed per product and order, with flying probe for prototypes and dedicated fixtures for volume. It checks netlist continuity and insulation resistance. It catches holes that are already open; it does not catch holes that currently conduct but have poor wall condition. Treating E-test as an assurance of hole-wall quality is the most common misconception in this area.
Thermal stress and solderability: cashing out latent defects. After solder float and thermal cycling, coupons are checked for barrel separation, delamination and plating peel. This is the method that forces latent drilling defects to declare themselves early, performed on sampled coupons.
Laser vias and mechanically drilled holes: where the criteria diverge
Below a certain hole size the inspection logic changes. The Sunking PCB multilayer capability figures are a 0.1mm minimum hole diameter and 0.075mm laser via diameter; single- and double-sided product families sit at a 0.3mm or 0.2mm minimum.
A mechanically drilled barrel is formed by cutting, so its defect family is burrs, smear, fibre protrusion and broken-bit debris, and inspection leans on magnified observation plus microsection. Laser-formed holes are usually blind vias that do not pass through the board, with a target copper layer at the bottom that has to be opened cleanly. The focus of judgement shifts from the wall to bottom-of-via connection quality: residual dielectric at the via bottom, over-etch of the target copper, and whether the via profile has a platable taper. Positional accuracy for these is no longer governed by a mechanical datum but controlled according to pattern density.
The practical implication for designers: if a board carries both mechanically drilled holes and laser vias, write acceptance criteria for the two classes separately. A single blanket "hole size ±0.003"" line forces clarification rounds during engineering review.
What can be re-evaluated and what is scrapped outright
This is the part quality engineers care about most and the part most often answered vaguely. The criterion is actually clear: ask whether the deviation is reversible, and whether it has already reached a level that cannot be reworked.
Cases that lean toward re-evaluation and possible engineering acceptance:
- Hole size at the tolerance edge but functionally adequate for assembly, with no tighter customer requirement on the drawing — measured data can be submitted for engineering release.
- Exit burrs and light smear found before desmear and hole metallisation — the downstream process itself includes the cleaning action.
- Outer-layer annular ring undersized but still adequate for solder joint reliability, with no inner-layer involvement.
- An isolated deviation on a single board, confirmed as a one-off rather than a batch trend by adding inspection points.
Cases that are scrapped and do not enter re-evaluation:
- A hole breaching inner-layer copper or drilling into a net that must not be connected. This is an inter-layer short with no rework path.
- Zero or negative inner-layer annular ring. The hole has lost effective connection to the inner pad, with no remedy after lamination.
- A microsection showing barrel separation or plating peel. Structural failure; re-measurement does not change it.
- Delamination after thermal stress testing. The material and lamination bond line are already damaged.
- Systematic hole-position offset out of tolerance. This is an equipment or datum problem rather than a one-off, and the whole batch needs re-evaluation.
- Broken-bit debris lodged in a hole that cannot be fully removed.
Note that "re-evaluation" does not mean "measure again and release." Done correctly, it means re-acquiring evidence with a method that can see the quantity in question, and filing the conclusion together with measured data in the job record. The Sunking PCB process control set has ten gates, with material and process records logged item by item into the job file — that is where traceability comes from.
Three things the design side can do to move drilling risk upstream
Drilling quality can only be detected in manufacturing, never created there. The actions that genuinely lower risk sit in design and data preparation.
One: define hole sizes unambiguously. State for every hole whether the figure is finished or drilled size, and define plated and non-plated holes separately in the drill file. Use consistent hole definitions and units across Gerber, drill, stack-up and impedance documentation — a rule already stated for resin-plugged via products that applies equally to ordinary through holes.
Two: leave pad margin for positional drift. Hole position tolerance is ±0.003", and annular ring design should take that as an input rather than adapting to it afterwards. Reserve inner-layer clearance at hole diameter +0.020" instead of reusing outer-layer rules.
Three: put acceptance criteria on the drawing, not in the receiving inspection conversation. If you have specific requirements on hole-wall condition, microsection scope, aspect ratio or particular holes, write them into the drawing at RFQ stage. Manufacturing organises the quality plan from the drawing; a requirement raised at receiving that was never on the drawing becomes a change, not a judgement. High-aspect-ratio holes, back-drilled holes and blind vias additionally need pad geometry, hole diameter, copper construction, aspect ratio and lamination sequence reviewed as one system, with the achievable window confirmed in engineering review. Submitting a complete data package with the RFQ compresses that clarification round to the minimum.
Material choice participates as well: different base materials respond differently to drilling depending on resin system and glass construction, and the laminates typically used on high frequency PCB builds are drilled and desmeared differently from standard FR-4.
Summary
Drilling quality is not a single pass/fail judgement. It is the result of four quantities — hole size, hole position, inner-layer hole-to-copper clearance and hole-wall condition — being evidenced at four different process points by four different methods. The dimensional quantities can be measured and re-evaluated; hole-wall problems, once formed, are largely irreversible. That is also why the cost curve for drilling defects is unusually steep: they occur at the earliest operation and surface at the latest one.
FAQ
Q1: Why is the plated-hole tolerance wider than the non-plated one?
Because a plated hole's finished size equals the drilled size minus barrel plating thickness, adding one variable. The Sunking PCB figures are plated holes (<0.247") ±0.003", non-plated holes (<0.250") ±0.002", larger holes ±0.005". When dimensioning, state whether the figure is finished or drilled size.
Q2: Does 100% electrical test guarantee hole-wall quality?
No. E-test checks netlist continuity and insulation resistance. It catches holes that are already open; it cannot catch a hole that currently conducts but has poor barrel plating condition. The complete hole-wall criterion comes from microsection; structural reliability is evidenced by thermal stress and solderability testing. E-test method is confirmed per product and order — flying probe for prototypes, dedicated fixtures for volume.
Q3: Can a mis-drilled hole position be corrected?
A dimensional drift within pad margin can go to engineering review. But if the hole breaches inner-layer copper, enters a net that must not be connected, or leaves a zero/negative inner annular ring, that is an inter-layer failure with no rework path after lamination, and it is scrapped. This is why the drilling gate uses a test coupon to check hole position relative to the inner layers.
Q4: When is a microsection mandatory?
Ordinary holes are covered by the post-plating non-destructive measurement of five or more points per panel. Heavy copper builds and high-aspect-ratio holes require an additional microsection, because the deeper and finer the hole, the more likely mid-barrel plating is thinner than at the entry, and non-destructive measurement cannot see mid-barrel. The microsection also covers layer registration, lamination bond line and plating structure.
Q5: Can laser vias and mechanical holes share acceptance criteria?
No, write them separately. Mechanical holes are judged on barrel morphology and size tolerance. Laser vias are mostly blind, and judgement centres on bottom-of-via connection quality — residual dielectric, target copper condition and platable taper — with positional accuracy controlled by pattern density. The multilayer figures are 0.1mm minimum hole diameter and 0.075mm laser via diameter, with specific structures confirmed in engineering review.
Q6: When should drilling-related acceptance requirements be raised?
At RFQ stage, on the drawing. Manufacturing builds the quality plan from the drawing, and an inspection item raised at receiving that was never documented is treated as a change rather than a judgement. Hole-wall criteria, microsection scope, aspect ratio requirements and back-drill or blind-via acceptance details all belong in this category.