"We need a ceramic PCB." By the time that sentence shows up in a design review there is usually a good reason behind it: power density has outgrown FR-4 and even metal-core boards, or the operating temperature is too high, or the CTE has to sit close to the die to survive thermal cycling. All valid. But that sentence is not yet a manufacturable decision.
A ceramic PCB is two things stacked on top of each other:
- The substrate system — what the white ceramic tile itself is made of: Al₂O₃ (alumina), AlN (aluminium nitride) or Si₃N₄ (silicon nitride). This layer decides how fast heat leaves, how brittle the board is, and which cost bracket you are in.
- The metallisation route — how copper got onto that ceramic: DPC (thin-film sputtering plus plating), DBC (direct bonded copper at high temperature), AMB (active metal brazing) or thick film. This layer decides how much current you can push and how fine a line you can draw.
These two layers are independent of each other. Take the same Al₂O₃ tile: what comes off a DPC line and what comes off a DBC line support completely different designs. Run the same DBC line with Al₂O₃ versus AlN and you get different thermal behaviour and different thermal-cycling life.
The most common way engineering teams hit a wall is by treating both layers as one vague "ceramic PCB" choice: the material gets picked for heat, the artwork gets drawn with FR-4 habits, and then someone points out that those fine lines cannot be etched in thick DBC copper. Or the reverse — every fine-line requirement is met, and then the tens-of-amps power loop will not fit through thin plated DPC copper.
This article crosses the two layers into one table and walks through what each combination locks down.
How this article differs from our ceramic overview guide
SKPCB already publishes a ceramic substrate PCB guide. That article answers "what kinds of ceramic PCB exist": it compares the thermal conductivity, CTE, strength and cost of Al₂O₃, AlN and Si₃N₄ side by side, then lists DBC, DPC, AMB and thick film in parallel with their typical uses, and closes with applications, advantages and disadvantages. If you need the panoramic view, read that one first.
This article does not repeat those comparison tables. It answers a different question: once you combine the two layers, which of my design freedoms are gone? So instead of listing options in parallel, it crosses material against metallisation and lands each combination in the boxes you actually have to fill on a drawing — minimum line width, current capability, thickness range, outline machining. If you already know AlN conducts heat better than Al₂O₃ and DBC carries more copper than DPC, but you are not sure *how to draw this revision*, this is the step after that guide.
Layer one: the substrate decides where heat goes, and how brittle the board is
Our ceramic PCB product page publishes the substrate system as Al₂O₃/AlN/Si₃N₄ with a thermal conductivity range written as 24-230 W/m·K. That span is close to an order of magnitude, which by itself tells you these three materials are not in the same class. Using the tiers published in our own ceramic substrate PCB guide:
| Substrate | Thermal conductivity | CTE (ppm/°C) | Mechanical strength | Relative cost |
|---|---|---|---|---|
| Al₂O₃ (alumina) | ~24 W/m·K | ~7 | Medium | Low |
| AlN (aluminium nitride) | ~170–230 W/m·K | ~4.5 | Medium | High |
| Si₃N₄ (silicon nitride) | ~70–90 W/m·K | ~3 | Very high | High |
(These figures are quoted from our published guide. They are generic material tiers, not SKPCB process control values; batch-specific material parameters are confirmed in the project documents.)
What matters in this table is not the ranking but the order-of-magnitude gaps across three different axes:
The thermal conductivity gap is the largest. Al₂O₃ to AlN is roughly 24 to 170-plus, more than 7×. So if your heat flux already sits at the Al₂O₃ boundary, moving to AlN is not an improvement — it is a different class of heat spreading. The reverse holds too: if Al₂O₃ is already sufficient, AlN buys you cost and nothing else.
The CTE gap decides thermal-cycling life. Silicon sits near 3. Al₂O₃ at ~7 is clearly mismatched against the die, and on every temperature cycle that difference in expansion is absorbed entirely by the solder layer and the bond interface in between. AlN at ~4.5 is closer; Si₃N₄ at ~3 is closest. So wherever thermal-cycle count is the dominant failure mode (automotive power modules, EV), the first selection criterion is not thermal conductivity — it is CTE and strength.
Strength decides machining and handling. Ceramic is brittle. The design considerations on the product page state it plainly: the ceramic outline is produced by dicing or laser rather than routing, so outline tolerance and whether break-apart panels are required must be specified separately. Si₃N₄ has markedly higher bending strength and fracture toughness, and that is its actual value in large, thin, heavily cycled parts — not "more thermally conductive" but less likely to crack.
One structural difference that often gets skipped: ceramic versus metal-core (MCPCB) is not just a material swap. An aluminium board has to put an insulating dielectric in the heat path, and that dielectric has to insulate and conduct heat at the same time — a genuine trade-off in itself (see the aluminium PCB insulation layer thermal trade-off and aluminium and metal-core PCB thermal management). Ceramic has no such layer: the ceramic body is both the insulator and the heat conductor. That is the structural advantage of ceramic over an aluminium PCB at high heat flux, and part of why it costs more.
Layer two: metallisation decides how fine the line is and how much current fits
Once layer one is settled, the white ceramic tile is still nothing usable — there is no copper on it yet. How the copper got there is a completely separate decision.
In the process flow published on the product page, step 1 is "confirm the substrate system (Al₂O₃/AlN/Si₃N₄), thickness and metallisation route", and step 3 is "build the metal layer to the selected process route and control adhesion". That ordering is not document formatting. It says the metallisation route is a first-class input alongside the material, not a downstream detail.
Our guide lists four main routes. Here we only open up the two that oppose each other in practice:
DPC (Direct Plated Copper) — a very thin seed metal is sputtered onto the ceramic surface, then electroplated up. The defining trait is that it is additive from the start, with pattern precision set by photolithography. Therefore:
- Line width and spacing can go fine. That is its home turf: miniaturisation, high-density packaging, carriers that need precise geometry.
- Because the copper is plated up, thickness growth has economic and process limits. High current is not its strength.
- It can metallise through-holes and blind vias, which is what makes interlayer connection on double-sided ceramic possible.
DBC (Direct Bonded Copper) — copper foil is bonded directly to the ceramic (usually Al₂O₃ or AlN) at high temperature. The defining trait is that it starts as a full sheet of thick copper. Therefore:
- Current carrying and heat spreading are strong. This is the mainstream route for IGBT-class power modules.
- The pattern is obtained by etching thick copper, so the minimum line width is clearly coarser than DPC: the thicker the copper, the harder the etched sidewall is to control, and fine lines stop being achievable.
- The CTE mismatch between thick copper and ceramic is more pronounced, which makes the route more sensitive to the substrate's strength and CTE. That is exactly why AlN and Si₃N₄ keep getting chosen with DBC and AMB in automotive work.
(AMB brazes copper to the ceramic with an active filler alloy for higher bond strength, and pairs particularly well with Si₃N₄ and heavy thermal cycling. Thick film prints and fires conductive pastes, suiting hybrid circuits and cost-sensitive power applications. Both are positioned in the guide.)
What is given here is direction, not numbers: DPC goes fine, DBC goes thick and high-current. We do not state a minimum line width or a maximum copper thickness per route, because those boundaries are constrained jointly by the substrate, thickness, pattern density and downstream machining, and have to be confirmed in engineering review. The ±0.02mm trace-width accuracy on the product page is a process precision figure — it is not a minimum achievable line width on every route, and the two should not be conflated.
Crossing the two layers: what each of the four combinations locks down
Crossed together, the four combinations engineering sees most often divide up like this:
| Combination | Typical driver | Freedom that is locked down |
|---|---|---|
| Al₂O₃ + DPC | Cost-sensitive, fine artwork, moderate heat flux | Heat spreading is capped by the Al₂O₃ conductivity tier; high-current paths can only be widened, not thickened |
| AlN + DPC | High heat flux plus dense fine lines (laser modules, sensors, semiconductor carriers) | Cost rises substantially; current capability is still bounded by plated copper thickness; AlN needs more care in machining and handling |
| Al₂O₃ + DBC | Mainstream power modules, controlled cost | Minimum line width is locked by thick-copper etching, so fine artwork is out; the Al₂O₃ CTE mismatch limits thermal-cycle endurance |
| AlN + DBC | High heat flux power modules that must spread heat *and* carry heavy current | Among the highest cost; fine lines still unavailable; thick copper on a high-conductivity substrate puts the most demand on bond interface and warp control |
The way to use this table is not to pick a cell. It is to check whether your design is asking for things from two different cells at once. The classic conflict: one revision containing both a signal or gate-drive area that needs fine artwork and a power loop that needs tens of amps. On a single metallisation route those requirements contradict each other — DPC gives you the fine lines but not the current, DBC the other way round.
The usual way out is partitioning: split the power section and the control section onto different substrates or different process zones, rather than forcing one route to satisfy both ends.
This conflict gets more expensive the later it surfaces. At RFQ stage it is one clarifying sentence. At prototype stage it is a redraw. Before volume it is a new set of fixtures and a new test plan.
Thickness and outline: the third constraint surface that gets missed
The product page publishes a thickness range of 0.25mm-2.0mm, surface roughness Ra≤0.4μm and temperature resistance -55°C~850°C. Thickness means something entirely different on ceramic than on FR-4:
- Thin substrates are not free. The design considerations state that thin substrates need handling and assembly stress considered, and recommend describing the downstream packaging and test method at RFQ stage. The thinner the ceramic, the higher the crack risk at every handling, die-attach and clamping step — and most of those steps happen outside the board shop. This is a constraint that runs all the way into your assembly line.
- The outline method is dictated by the material, not by the design. Dicing runs straight cuts; laser can follow a contour but leaves a heat-affected zone. So the irregular outlines, internal slots and small radii you would sketch freely on FR-4 need re-evaluating on ceramic, and outline tolerance must be called out separately (see the published ranges on our manufacturing tolerance page).
- Metal layer thickness, trace and spacing intent, and adhesion requirements must be submitted together. The product page bundles those three into a single requirement precisely because of the two-layer decision above: give engineering a line width without a copper thickness and there is no way to judge which metallisation route is viable.
What each layer has to say in the engineering review package
The product page lists the review package as: Gerber or ODB++, drill data, stack-up, material and copper requirements, the plugging layer and acceptance criteria. Mapped onto the two ceramic decisions, here is what that concretely means:
Layer one (material)
- State the substrate system and thickness on the drawing. The design considerations say directly that Al₂O₃, AlN and Si₃N₄ differ in thermal, mechanical and machining behaviour and are not interchangeable — so "ceramic PCB" alone is not a specification.
- For high-power or hermetic applications, supply the heat-dissipation condition, thermal-cycle profile and hermeticity acceptance criteria. These three are the inputs that decide how CTE and strength get weighted; without them engineering is guessing.
Layer two (metallisation)
- Metal layer thickness requirement, and whether an alternative process route is acceptable.
- The intent behind trace and spacing: which are genuinely minimum lines and which simply came out that way. This determines whether the fine-line requirement is a real constraint or a relaxable one.
- Adhesion requirements and the test method that goes with them.
- Surface finish requirement (see the surface finish page).
Acceptance side
- The product page's outgoing inspection covers dimensions, appearance, adhesion and flatness. Flatness (warp) is particularly critical on thick copper over ceramic and belongs in the acceptance criteria, not in an argument at incoming inspection. For the quality system and inspection arrangements see quality assurance; for overall process boundaries see the capabilities overview and the materials library.
To have engineering confirm whether a specific combination is buildable, submit the package through quote and engineering review.
The two decisions in one block
Layer one selects where heat goes and how brittle the board is (Al₂O₃ is cheap and often sufficient; AlN buys a heat-spreading class; Si₃N₄ buys crack resistance and thermal-cycle life). Layer two selects how much current you can push and how fine a line you can draw (DPC toward fine, DBC toward heavy current). The layers are independent and must be specified separately. When one revision demands both fine lines and heavy current, the answer is to partition — not to force a single process route to cover both ends.
FAQ
Q: How do I actually choose between Al₂O₃ and AlN?
A: Start by asking whether your heat flux is already at the Al₂O₃ boundary. Per the tiers published in our guide, Al₂O₃ is around 24 W/m·K and AlN around 170–230 W/m·K, more than 7× apart. If Al₂O₃ still has margin in your thermal budget, AlN mainly buys cost. If the heat flux has already exceeded it, AlN is a step change rather than a tweak. The second criterion is thermal cycling: AlN's CTE (~4.5) sits closer to silicon than Al₂O₃'s (~7). The real choice is reviewed together with power density, package construction, thermal-cycle conditions and the machining route.
Q: Can DPC and DBC be mixed on the same board?
A: Mixing two metallisation routes on one substrate is not standard practice. The more common answer is to partition by function: put the fine-line control or signal section and the heavy-current power section on separate substrates, or separate them at system level. If your design carries both requirements, state the specific range of each at RFQ stage so engineering can assess whether partitioning is needed.
Q: Why not just publish the finest line DPC can do and the thickest copper DBC can take?
A: Because neither is a single number. Minimum line width and usable copper thickness are bounded jointly by the substrate material, substrate thickness, pattern density, the outline machining path and the downstream assembly method — change any one and the boundary moves. What the product page does publish are verifiable process precision figures (±0.02mm trace-width accuracy, 0.25mm-2.0mm thickness, Ra≤0.4μm). Route-specific capability is confirmed by engineering review of a submitted package, which is exactly why the page states that the process route is confirmed from that package rather than by applying unverified generic limits.
Q: When is Si₃N₄ worth the premium?
A: When the dominant failure mode is cracking or thermal-cycle fatigue rather than insufficient heat spreading. Per the published tiers, Si₃N₄ conducts less heat than AlN (~70–90 W/m·K) but has the highest bending strength and fracture toughness and the CTE closest to silicon (~3). Large, thin, heavily cycled parts — automotive and EV power modules — are its typical home. If the problem is purely heat flux, AlN is usually the more direct answer.
Q: What is the fundamental difference between ceramic and metal-core (MCPCB)?
A: Structurally, the insulation layer. On an aluminium board the heat must first cross a dielectric that has to insulate and conduct at the same time; that dielectric is the bottleneck in the whole thermal path and an explicit trade-off. A ceramic substrate insulates and conducts by itself, so there is no such layer. That is the structural advantage of ceramic at high heat flux, paid for in material cost and machining constraints (brittleness, dicing or laser outlines). For the aluminium trade-off see aluminium PCB insulation layer thermal trade-off and aluminium and metal-core PCB thermal management, and the aluminium PCB product page.
Q: How thin can a ceramic board go?
A: The product page publishes 0.25mm-2.0mm. But "how thin can it be made" and "how thin can it be used" are separate questions: the thinner it gets, the higher the crack risk at dicing or laser profiling, handling, die attach and clamping — and most of that risk lives outside the board shop. The page's own recommendation is to describe the downstream packaging and test method at RFQ stage so manufacturability and assemblability are reviewed together.