1. What makes plating different: it is the first step that develops every upstream defect
When drilling finishes, a hole looks acceptable. Diameter sits inside the ±0.05 mm hole tolerance, position inside ±0.025 mm, the machine has already verified the diameter automatically, and a dedicated test coupon has checked hole position against the inner layers. But as our drilling hole quality inspection article opens by stating, most drilling defects only surface after plating. Burrs, resin smear and protruding glass fibre in the barrel are not necessarily visible in a dry hole, yet they turn into discontinuous plating, thin barrel copper or poor adhesion once the panel goes through the plating line.
That is where this gate sits. It has to judge its own process, and it simultaneously acts as the developer for upstream drilling and lamination quality.
Among the ten in-process inspection points on our quality assurance page, point 07 is copper and tin plating: non-destructive sampling at five or more points per production panel, with heavy copper builds and high-aspect-ratio holes getting an additional microsection to confirm hole-wall copper uniformity. Two sentences — but they answer two entirely different questions. This article unpacks both, including what each can and cannot prove.
> Division of labour with the target page: the quality assurance page gives the full picture of all ten checkpoints and the system around them (IPC-A-600 Class 2, UL796, job quality records, traceability). This article expands point 07 alone into release logic you can verify and request.
2. Two bodies of evidence, two different questions
Sampling (five or more points per production panel, non-destructive) answers "is there enough, and is it evenly distributed?"
It is per-panel, full-coverage and repeatable. The two phrases that matter are "per production panel" and "five or more points". The first means it is not batch sampling of panels — every production panel is measured. The second means a single passing point does not count; readings have to form a distribution across the panel. The characteristic plating failure mode is not uniform thinness across a whole panel, it is uneven distribution across the panel surface — edge versus centre, dense areas versus open areas plate at different rates. One measurement cannot see that. A distribution can.
The price of being non-destructive: it measures surface copper, and it cannot reach inside the hole.
The microsection answers "what does the inside of the barrel look like?"
Microsections are destructive, so per the quality page they are run on test coupons that travel with the panel, never on your finished boards. Each coupon runs the identical process in the same batch as the production panel, so measuring the coupon measures the board. Four things are judged: hole-wall copper thickness, layer registration, the lamination bond line, and plating structure.
The first three are physically out of reach for surface sampling. The fourth, plating structure, matters most — it is not about a thickness number but whether the deposit itself formed correctly: no inclusions, no voids, no adhesion failure. A barrel that meets thickness but has a structural defect passes sampling.
So the two are not redundant, they are a division of labour. Sampling guarantees coverage (every panel). Microsections guarantee depth (they see inside the hole). Neither substitutes for the other.
3. Why the added microsection is scoped to heavy copper and high-aspect-ratio holes
The quality page is specific about what triggers a microsection: heavy copper builds and high-aspect-ratio holes. Neither is arbitrary; each corresponds to a physical reason plating struggles to stay uniform.
| Trigger | Capability figure on site | Why plating goes uneven here |
|---|---|---|
| Heavy copper | Capabilities copper weight 0.5oz->12oz | The target range is enormous. One process family has to reach from 0.5oz to over 12oz; the heavier the target, the more it depends on stable time and distribution, and the absolute value of any deviation scales with it |
| High aspect ratio | Aspect ratio 10:1 max, min hole 0.075 mm, mechanical drill min 0.15 mm | The deeper and narrower the hole, the harder solution exchange becomes at mid-barrel. Thicker at the entry and thinner mid-barrel is the inherent tendency of these holes |
10:1 max is a ceiling, not a comfort zone. A 2.0 mm board with 0.2 mm holes is exactly 10:1 — already on the line. The same thickness with 0.3 mm holes is roughly 6.7:1, and far easier. The same word "pass" costs very different amounts to achieve at those two aspect ratios, which is precisely why high-aspect-ratio holes owe an extra piece of evidence.
On the design-side inputs behind copper: HDI build-up and copper plating thickness design inputs covers which three copper numbers belong on the drawing, and copper thickness options and design rules covers the available tiers. This article covers how manufacturing proves it met them once those numbers are written down.
4. Why hole-wall copper defects cannot be deferred to electrical test
This is the most important point here, and the most commonly misread.
Final electrical test — per point 10 on the quality page, with the applicable method confirmed per product and order, flying probe for prototypes and a dedicated fixture for volume — judges netlist continuity and insulation resistance. It asks whether the net conducts.
A barrel with thin but continuous copper passes electrical test, because under the ambient, unstressed conditions of that test it genuinely does conduct. The problem arrives later: its margin has been consumed, and it cracks under reflow thermal shock or during temperature cycling after assembly. By then the board carries components and sits on your customer's line.
The quality page's thermal stress and solderability testing shows how this is handled: solder float and thermal cycling on test coupons, then inspection for barrel separation, delamination and plating peel. Note those three terms — none of them is a failure mode electrical test can see, and all of them require destructive checking before shipment to expose.
So the nature of this gate is: it does not judge whether the net conducts now, it judges whether it will still conduct later. That judgement can only be made here, because further downstream the barrel is buried under solder mask, surface finish and routing, and there is no way to look inside except through a destructive coupon.
Where exactly is the no-rework line? Two layers to it:
- After lamination, inner layers cannot be reworked. Point 04 on the quality page states this outright, and it is the reason inner-layer AOI must stop every imaging defect before pressing.
- After plating, the inside of the hole cannot be repaired. Once barrel copper has formed, there is no way to re-plate one individual hole without destroying the board. Outer-layer copper still has a downstream checkpoint (point 08: a test coupon on every production panel verifies trace width, with
±20%trace-width tolerance per our tolerance table), but the copper inside the hole is final at this step.
5. Which design inputs raise the difficulty of this gate directly
All of the following come from the figures on our capabilities page, not estimates. What they share: on a drawing each is just a number, but at the plating step each is a difficulty multiplier.
- Aspect ratio approaching 10:1. Board thickness and hole size multiply. The half designers most often overlook is thickness — taking a 1.6 mm board to 3.0 mm doubles the aspect ratio of every small hole at once.
- Copper targets at the high tiers.
0.5oz->12ozis the capability span, but releasing >12oz and releasing 1oz are not the same order of difficulty. Heavy copper necessarily triggers the added microsection. - Mixing min hole
0.075 mm(laser) with0.15 mm(mechanical). When one panel carries both laser microvias and deep mechanically drilled holes, a single plating recipe has to satisfy two geometries — the difficulty compounds rather than adds. - Min trace/space
2mil/2mil. Outer-layer copper thickness and fine-line width are mutually limiting: the thicker the plate-up, the harder fine lines hold the±20%trace-width tolerance. - Impedance
±5% (±10% std). See impedance control PCB. Copper thickness is one input to impedance, so uneven distribution moves two things at once and both tolerances have to close together. - Any-layer, blind/buried vias, resin plug, copper paste fill. These constructions mean plating forms across multiple lamination and fill cycles, and every cycle is another release decision.
6. What you can ask the factory for
This section is where the article earns its keep. Per the job quality record scope on the quality page, each order's inspection results are consolidated into its own job record: laminate grade and batch, measured values at each checkpoint (copper thickness, post-lamination thickness, impedance, outline tolerance) and the tests it passed, with the full production record available on request.
Narrowed to the plating step, the concrete asks are:
- The measured copper thickness record for your order, corresponding to the five-or-more-point per-panel sampling in point 07. Ask for that batch's record, not a generic capability statement.
- The microsection report, if your board is heavy copper or high aspect ratio. Ask explicitly which of the four it judged: hole-wall copper thickness, layer registration, lamination bond line, plating structure.
- A statement on how coupons travel with the panel. The quality page states destructive tests run only on coupons, and that each coupon runs the same process in the same batch. That sentence is the entire basis for a microsection report representing your board — worth confirming at RFQ stage.
- Thermal stress and solderability results, where applicable. Solder float and thermal cycling, then inspection for barrel separation, delamination and plating peel. This is the evidence for "will it still conduct later".
- The applicable standard and class. The quality page states IPC-A-600 Class 2 and UL796; capabilities lists IPC-A-600 Class 2/3. Class 2 and Class 3 acceptance requirements differ and must be confirmed during engineering review and quotation, never assumed.
For the principles and scope of the inspection methods themselves, see PCB quality inspection methods; for the criteria at the outer-layer imaging step, see the outer layer pattern inspection checklist.
7. FAQ
Q1: How is five sampling points decided, and why not more?
The quality page states non-destructive sampling at five or more points per production panel — five is a floor, not a quota. The actual count and locations follow that order's board type, copper tier and aspect ratio, and are confirmed during engineering review and quotation. The logic mirrors lamination: the higher the layer count and the thinner the dielectric, the tighter the sampling.
Q2: If non-destructive sampling cannot reach inside the hole, why do it at all?
Because it is the only method that achieves per-panel, full coverage. Microsections are precise but destructive, so they can only sample. Sampling covers everything but only reaches the surface. Release needs both: coverage from sampling, depth from microsections.
Q3: My board is neither heavy copper nor high aspect ratio — does that mean no microsection evidence?
The quality page scopes microsections as an addition for heavy copper and high-aspect-ratio holes, not as routine for every board. That said, microsections are also the criterion for multilayer layer registration and the lamination bond line, and the vehicle for thermal stress testing. Whether yours needs one follows your board type, applicable standard class and order requirements, confirmed at engineering review.
Q4: We do 100% electrical test — doesn't that cover hole problems?
No. Electrical test judges netlist continuity and insulation resistance, meaning whether the net conducts now. A barrel with thin but continuous copper passes it, and can still crack under reflow thermal shock or post-assembly temperature cycling. That failure class is exposed before shipment by coupon-based thermal stress and solderability testing looking for barrel separation, delamination and plating peel. Electrical test does not substitute.
Q5: Can a board with out-of-spec plating be saved?
It depends where. Once copper inside a hole has formed, there is no way to re-plate one hole without destroying the board. Outer-layer copper still has a downstream judgement point (point 08, coupon trace-width verification on every panel). That asymmetry is exactly why plating is treated as a release gate rather than an intermediate step.
Q6: Is surface finish thickness the same thing as plated copper?
No. Copper and tin plating is point 07. Surface finish thickness (HASL, lead-free HASL, ENIG, OSP, immersion tin, hard gold — see surface finish) is checked at point 09 together with solder-mask registration and thickness; the quality page's own example is gold and nickel thickness on ENIG. Two gates, two different layers, separately recorded.
