Separate "level count" from "layer count" first
These two numbers often appear in the same sentence, yet they constrain entirely different things.
Layer count is a spatial quantity: how many copper layers the board has. Level count is a temporal quantity: how many passes the outer buildup structure was built in.
Two 10-layer boards, 1+8+1 and 3+4+3, are different products:
1+8+1— an 8-layer conventional core with one buildup layer per side. The outer structure runs once.3+4+3— a 4-layer core with three buildup layers per side. The outer structure runs three times.
Same layer count, possibly similar finished thickness, but the second board passes through two additional complete lamination-and-plating cycles. Every cost discussed below comes from those extra passes, not from the layer count.
SKPCB's layer capability is 40 layers in standard production and 64 layers maximum; the HDI level capability is up to 5 levels (5+N+5), classified as production-capable rather than R&D. These are two independent capability lines and do not convert into each other.
> If your actual question is how many layers are achievable and what constrains high-layer-count boards, that is a separate topic: see high layer count PCB constraints from 40 to 64 layers. This article is about levels only.
One level equals one complete cycle
Sequential lamination means the buildup cannot be pressed in a single shot. It is added one pass at a time, and each pass is a complete manufacturing cycle:
| Step within a pass | What this pass is doing | Equipment on record |
|---|---|---|
| Lamination | Press new dielectric and foil onto the completed structure | Burkle vacuum lamination press |
| Laser drilling | Drill this level's microvias in the new layer | Han's Laser drilling machine |
| Hole metallization | Make the newly drilled microvia walls conductive | — |
| Plating | Build up via copper and surface copper | Atotech VCP vertical continuous plating |
| Imaging | Write this layer's pattern into the copper | Orbotech LDI laser direct imaging |
| Etching | Remove copper outside the pattern | — |
| AOI | Release inspection for this level | Orbotech AOI |
The point is this: these seven steps are not distributed across the levels. Every level runs all seven. A 3-level board runs the table three times; a 5-level board runs it five times.
And there is an asymmetry worth holding onto: the outermost layer participates in every pass. Inner levels are finished and then buried, but the outer copper surface sees another plating cycle in every subsequent pass. That asymmetry is the common root of all three costs below.
Cost one: accumulated outer-layer plating passes rewrite minimum trace width
Outer copper is not plated to final thickness in one step. It is the accumulation of every pass's plating.
So the more levels, the thicker the outer copper already is before imaging. And the thicker the copper, the harder it is to control side etch, which pushes the reliably achievable minimum trace width and spacing in the conservative direction.
SKPCB's trace capability has three tiers: standard 4/4 mil, advanced 3/3 mil, R&D 2/2 mil (advanced and R&D tiers both require engineering review). Those tiers are not simultaneously valid at every level count. Asking for 2/2 mil outer traces on a high-level board is a different difficulty class from asking for 2/2 mil on a single-level board.
The practical conclusion is blunt: level count and fine outer-layer traces are two demands that squeeze each other, and you cannot take both to the limit. A design that needs 5 levels and the finest outer trace width at the same time is not a quoting question, it is an engineering review question.
> How to specify outer copper thickness itself — which of starting foil, post-plate finished copper and microvia copper is determined by whom — is covered in full in HDI buildup copper and plating thickness design inputs. This article does not repeat it, only notes the coupling.
Cost two: registration error accumulates per pass, it does not reset
Every lamination pass has to register the new layer to the already-completed structure, and that registration action carries its own tolerance.
The intuitive assumption is that re-registering each pass resets the error. The opposite is true: each pass can only register to the previous pass's actual result, not to the design origin. Whatever offset the previous pass produced, the next pass carries it forward and keeps building on top of it.
So the more levels, the larger the accumulated offset of the outermost layer relative to the innermost core. On a finished board this shows up as:
- Microvias landing eccentric on the target pad below, leaving insufficient annular ring
- Stacked via structures where upper and lower vias are not concentric
- Impedance-controlled traces sitting at a different actual position relative to the dielectric than designed
SKPCB's hole position accuracy is ±0.05 mm (normal), with hole size tolerance PTH ±0.075 mm, NPTH ±0.05 mm. These are single-operation figures. There is no "accumulated registration error over N levels" entry on record, so any linear extrapolation of accumulated offset by level count is not a citable capability. Registration margin on high-level boards must be confirmed in engineering review against the actual stackup.
One clarification about the X-ray drilling target machine (Pluritec): it exists to measure where the inner-layer targets actually ended up, so the drill program can register to the real structure. It does not correct offsets from earlier passes. An offset already pressed into the structure cannot be pressed back out.
Cost three: shrinkage compensation must be set per pass
A core expands and contracts in every lamination thermal cycle, and that amount is not a fixed material property. It depends on what the core has already been through before this pass: residual copper distribution, the number of thermal cycles already seen, current structural stiffness.
The consequence: the same material part number needs different compensation factors in pass one and in pass three. Fixing one compensation value per part number may be adequate on a single-level board; on a high-level board it will miss on some pass.
This is the real process-management requirement that high-level HDI imposes: compensation parameters have to be managed per pass, not per material. There is a limit to what the design side can do about it, but one thing matters a great deal — supply a symmetric stackup with balanced residual copper, which materially reduces how unpredictable each pass's shrinkage is.
> Void and delamination mechanisms in lamination itself are a separate subject: see lamination void and delamination prevention.
How level count limits available via types and sizes
Levels are not only a cost. They also constrain which vias you can use.
- Laser microvia diameter — SKPCB standard minimum 0.1 mm; advanced and R&D tiers 0.075 mm (engineering review required).
- Mechanical holes — standard 0.2 mm, advanced and R&D 0.15 mm.
- Maximum PTH aspect ratio — 10:1.
- Any-layer interconnect and buried/blind vias — up to 12 layers (both conditional, engineering review required).
Aspect ratio deserves attention: on a thick board with many levels, the through-hole aspect ratio often hits its ceiling before the level count does. SKPCB's thickness range is 0.2–6.0 mm, and near the upper end of that range the first thing to block you is usually aspect ratio, not level count.
As for stacked versus staggered microvias — that choice is tightly coupled to level count but is its own decision and is not expanded here. Individual microvia aspect ratio and via copper are covered in laser-drilled microvia plating and aspect ratio; impedance tolerance classes and test scope are on the impedance control PCB page.
Decision criteria: add a level, switch to any-layer, or change the design
Work through these in order when setting level count:
- Does the BGA escape genuinely need this many levels? Level count is usually set by the densest BGA on the board. Confirm its pitch and pin count really cannot be escaped otherwise — adjusting the fanout strategy sometimes removes an entire level.
- Is this level being added for a handful of nets? If so, a whole pass is being paid for by a few connections, which rarely pays. Reconsider the routing.
- Are you close to the structural ceiling? SKPCB is production-capable to 5 levels (
5+N+5). Near that ceiling, anany-layerstructure (up to 12 layers, engineering review required) may be the better path than stacking more levels. - Do you still want the finest outer traces? If high level count and finest outer trace width are both required, return to cost one — one of them has to give.
- Can the schedule absorb it? Verified figures on record: 6-layer single-level HDI prototype in 48 hours; 10-layer two-level HDI (10 m²) in 10 days; 8-layer any-layer in 6 days. Level count affects lead time in steps, not linearly.
HDI inputs that must accompany the drawing
| Input | Why it is required | Consequence if omitted |
|---|---|---|
Explicit level notation (e.g. 2+N+2) | Layer count alone does not imply level count | The factory quotes the cheapest structure, which is not your design |
| Full stackup with intended dielectric and copper per layer | Basis for dividing passes | Pass division gets decided for you |
| Microvia diameter and target pad per level | Determines diameter tier and registration margin | Out-of-capability microvias surface late |
| Stacked or staggered requirement | Coupled to level count | Defaults to whichever is easiest to build |
| Impedance requirement and tolerance class (±10% or ±5%) | ±5% is conditional and needs review | Unreachable tolerance surfaces in production |
| Minimum outer trace width and spacing | Squeezed against accumulated plating passes | Fine traces and level count both at the limit means rework |
| Thickness and total thickness tolerance intent | Interacts with aspect ratio and level count | Aspect ratio hits the ceiling first |
| Acceptance class (IPC-A-600 Class 2 or 3) | Sets annular ring and via copper criteria | Criteria disputes land at final inspection |
Full capability tiers are listed on manufacturing capabilities, acceptance and test scope on quality assurance, and product-side structure on the HDI PCB page.
FAQ
Q: Where does the price difference between a 10-layer HDI and a 10-layer conventional multilayer come from?
A: From passes. A conventional 10-layer board presses its outer structure once; a 10-layer 3+4+3 HDI runs the outer structure three times, each pass including lamination, laser drilling, metallization, plating, imaging, etching and AOI. For actual cost differences, go through the quoting process — this article does not publish multipliers.
Q: Does more levels always mean worse registration?
A: Accumulated offset growing with pass count is structural, but how much worse cannot be linearly extrapolated from level count. SKPCB's ±0.05 mm (normal) hole position accuracy is a single-operation figure. Actual registration margin on a high-level board must be confirmed in engineering review against the specific stackup.
Q: Can X-ray targeting correct offsets from earlier passes?
A: No. It measures where inner-layer targets actually are so subsequent drilling registers to the real structure. An offset already laminated into the structure cannot be reversed.
Q: What is the maximum level count?
A: SKPCB is production-capable to 5 levels (5+N+5), classified as production rather than R&D. Near that ceiling, evaluate any-layer construction in parallel (up to 12 layers, engineering review required).
Q: I need 5 levels and 2/2 mil outer traces at the same time. Is that feasible?
A: 2/2 mil sits in the R&D tier and requires engineering review; combined with 5 levels the two requirements squeeze each other. Submit both requirements together with the stackup for engineering review rather than ordering each at its individual limit.
Q: Why can't shrinkage compensation be fixed per material part number?
A: Shrinkage depends on the thermal cycles already seen, residual copper distribution and structural stiffness of that core before the current pass, all of which change per pass. One fixed value per part number may hold on a single-level board but will miss on some pass of a high-level board.