One hole, two unrelated ceilings
A microvia has to pass two independent gates, and they govern different things:
| Laser hole formation | Hole-wall metallisation and plating | |
|---|---|---|
| Decides | Whether the hole opens at all: minimum diameter, hole shape, positional accuracy, whether the target copper survives | Whether the hole can be covered: copper continuity at the bottom and corner, thickness at the thinnest point |
| Governed by | Spot size, pulse energy, absorption difference between dielectric and copper | Mass transport and current distribution, both degraded by depth-to-diameter |
| Published site data | Laser minimum hole 0.075 mm, position accuracy ±0.025 mm (capabilities) | Wall copper belongs to the plating vocabulary — see HDI copper thickness design inputs |
| Failure signature | Undersized hole, excessive taper, target pad not exposed, damage to the target layer | No copper at the bottom, thin corner copper, cracked plating, open after thermal cycling |
The first gate is geometric. The second is electrochemical. Aspect ratio presses on the second one.
What the laser actually limits: the hole is a cone, not a cylinder
Treating a microvia as a cylinder is where most miscalculations begin. Laser ablation removes material layer by layer from the surface, pulse energy attenuates with depth, and the wall therefore carries a taper — wider at the top, narrower at the bottom.
Three consequences follow:
- Diameter is two numbers, not one. A drawing that states "0.1 mm" has not said whether that is the top or the bottom. The HDI product page publishes a laser via diameter of 0.075 mm and microvia diameter ≥0.1 mm as capability floors; how top and bottom diameter are allocated on a given project follows from dielectric thickness and needs engineering review.
- Deeper holes lose more bottom. Taper is roughly constant, so added depth shrinks the usable bottom area quickly. The bottom diameter is the dimension that plating coverage and joint reliability actually live on.
- The target layer has to stop the beam. The floor of a microvia is the next copper layer, so the laser must clear the dielectric and stop. The absorption difference between dielectric and copper is the physical basis for that, which makes dielectric material and thickness uniformity direct contributors to hole consistency — material systems are listed on the materials page.
The laser can almost always go deeper. It simply produces a hole with a smaller, harder-to-plate bottom.
What the plating actually limits: mass transport and current distribution
Hole-wall metallisation has to accomplish two things inside a deep, narrow cavity that is open at one end only: exchange chemistry in and out, and distribute current evenly across every part of the wall. A higher aspect ratio degrades both at once.
- Mass transport. The bottom of a blind hole is not where flow happens. The larger the aspect ratio, the stronger the concentration difference between the hole mouth and the hole bottom, and deposition rate stratifies with it.
- Current distribution. The field favours the hole mouth and any protruding corner; current density at the bottom and at the wall root runs low. The mouth plates faster than the floor, and the corner becomes the thinnest point in the whole hole.
- The thinnest point governs acceptance. Wall copper is not accepted on an average; it is accepted at its minimum. Under thermal cycling, stress concentrates at geometric transitions, so the thinnest point and the highest-stress point tend to coincide. That is why microvias fail at the bottom corner in reliability testing.
So the full meaning of an aspect-ratio limit is this: beyond some depth-to-diameter, coverage at the bottom corner can no longer be held to the acceptance thickness with confidence. It is a statement about plating capability, expressed in a geometric unit.
Microvias and through-holes are two systems: 10:1 does not transfer
The 10:1 aspect ratio on the capabilities page describes mechanically drilled plated through-holes: open at both ends, larger in diameter, chemistry convects right through, waveform and agitation can be used to even out distribution. A microvia is the opposite case — a shallow blind hole closed at one end, supplied by diffusion rather than convection.
- Industry definitions of a microvia carry an aspect-ratio constraint in the definition itself: the IPC-2226 / IPC-6012 framework confines microvias to a far more conservative depth-to-diameter range than through-holes, on the order of 1:1 (industry specification, not a Sunking internal window; the governing criteria are the standard revision cited on the drawing).
- The published 10:1 is a through-hole figure and is not a microvia commitment. Microvia manufacturability is confirmed per build-up through engineering review.
- Both can coexist on one board: through-holes for power and thick-board interconnect, microvias for high-density fan-out, each accepted under its own criteria. For conventional multilayer through-hole cases see the multilayer PCB page and the stackup design guide.
Writing a through-hole 10:1 into a microvia requirement gets the package returned. This is not conservative versus aggressive — they are two different physical mechanisms.
Working backwards: how this bounds dielectric thickness and build-up level
This is the part the design side should take away. Microvia aspect ratio ≈ dielectric thickness ÷ via diameter, which locks three quantities together:
- Dielectric thickness is the numerator. Thickening the dielectric for impedance or dielectric strength deepens the hole and raises the aspect ratio directly.
- Diameter is the denominator, but it is not free. Enlarging the via to pull the ratio back also enlarges the capture pad, which consumes the routing space that motivated HDI in the first place. The mutual constraint between diameter, copper thickness and trace width is covered in HDI copper thickness design inputs.
- The real control is layering, not depth. When more layers have to be crossed, the correct answer is more build-up levels with stacked or staggered vias transitioning layer by layer, not one deeper hole. The HDI product page publishes 1+N+1 to 5+N+5 build-up structures with ±25 μm layer-to-layer registration — registration capability is the precondition for any stacked-via scheme, and it is also why build-up levels are not added indefinitely.
A workable order of operations: fix dielectric thickness per layer from impedance and dielectric-strength needs, derive the feasible via diameter from that thickness, then check whether the capture pad still fits the routing channel. When the three conflict, adjust build-up level and layer assignment first; change dielectric thickness last. Process-side constraints are outlined in HDI manufacturing process.
What the drawing package has to state
"Microvia 0.1 mm" is not a manufacturable requirement. At minimum, add these so engineering review has something to judge:
- Which diameter is specified — top or bottom, each with its tolerance. Hole size and position tolerances are on the tolerance page.
- Layer pair per via — start layer and target layer against the build-up table, with stacked versus staggered drawn explicitly.
- Dielectric thickness and its tolerance — it drives hole depth, so overall board thickness alone is not enough.
- Fill requirement — whether planarisation is needed, the planarity datum and the acceptance method. Details in resin filled via acceptance and on the resin plugged via PCB page.
- Standard and revision cited — where microvia criteria follow IPC, state the standard number, revision and class so nothing falls to a default.
- Wall copper requirement — state the requirement rather than the process, judged at the thinnest location.
Verification: microsection decides, appearance cannot
The critical dimensions and the critical failures of a microvia are inside the board, and neither visual nor automated optical inspection reaches the copper in the bottom corner.
- Microsection is the primary method. It yields hole shape, taper, copper continuity at the floor and thickness at the thinnest corner. Section locations have to be agreed with engineering and written into the package, otherwise a cut through the hole centre misses the thinnest point.
- Thermal stress and thermal cycling test continuity of the thinnest point under temperature load. That is reliability sampling, not a 100% screen.
- State the limits of bare-board testing. Electrical test finds connections that are already open; it does not find a thin-wall via that conducts now and opens after thermal cycling. That gap cannot be closed by substituting electrical test for microsection. Methods and rejection criteria are covered in PCB drilling quality inspection and on the quality page.
One line to close on: microvia reliability is fixed in design by the aspect ratio chosen; inspection only develops the image of that decision.
FAQ
Q: We cannot get the microvia depth we need — is laser power the issue?
A: Usually not. The laser can open a deeper hole, but the hole is tapered, so a deeper hole has a smaller bottom, and plating coverage at the floor and corner becomes the binding constraint. The ceiling sits on the plating side.
Q: The capabilities page states 10:1, so why can a microvia not be designed to 10:1?
A: 10:1 describes mechanically drilled plated through-holes — open at both ends, convection-fed. A microvia is a blind hole closed at one end and supplied by diffusion; industry criteria put it on the order of 1:1 (IPC framework, industry specification). The two figures are not interchangeable.
Q: Does enlarging the via diameter solve the aspect ratio?
A: Geometrically yes, at the cost of a larger capture pad and lost routing space, which erodes the density advantage HDI was chosen for. Where many layers must be crossed, adding build-up levels is the sounder move.
Q: Should the dielectric simply be made thinner?
A: Not on via considerations alone. Dielectric thickness also sets impedance and layer-to-layer dielectric strength, so thinning it in one direction breaks the electrical design. Fix electrical requirements first, then derive feasible diameter and build-up level.
Q: Where do microvias typically fail?
A: At the hole floor and the wall corner. Current density is lowest there and plating thinnest, and it is also where thermal stress concentrates — two unfavourable factors at the same location.
Q: What happens if the drawing only says "microvia 0.1 mm"?
A: Top/bottom diameter convention, layer pair, dielectric thickness, fill requirement and standard revision all fall to defaults, engineering cannot assess manufacturability, and the package is normally returned for clarification.
Q: Stacked or staggered vias — how is that chosen?
A: It is a trade between density and process margin, tied directly to registration capability (the HDI product page publishes ±25 μm). It has to be confirmed per build-up through engineering review; this article does not offer a universal answer.
To confirm whether a specific HDI build-up, microvia aspect ratio and diameter combination is manufacturable, send the stackup table, via table and drill files for DFM and capability review: request a quote.
