1. Why the board remembers where the copper was
FR-4 is resin plus glass cloth. Copper is metal. Their coefficients of thermal expansion are not in the same range, and that is where the whole thing starts.
Lamination is a cycle: heat up, apply pressure, cure, cool down. During heat-up the prepreg resin flows and fills; during cool-down the cured resin shrinks. Copper barely participates in that shrinkage — the resin does. So the actual shrinkage of each layer depends on how much copper is left on it. Copper-heavy regions pin the resin down. Copper-sparse regions shrink freely.
If the board is symmetric top to bottom and the copper distribution is symmetric with it, those shrinkage forces cancel and the board comes out flat. The moment symmetry breaks, whatever does not cancel stays inside the laminate as internal stress. Internal stress does not disappear. It waits for an opportunity to deform and release — possibly right after lamination, possibly under the thermal shock of drilling, profiling or surface finishing, sometimes not until reflow at the customer's assembly line.
That is why warpage is an accumulated problem rather than a single-step defect. It is not one operation done wrong; it is several small asymmetries stacking in the same direction.
2. First kind of asymmetry: copper retention within a single layer
Start inside one layer. On an inner layer, the copper retention of a solid plane region and a densely routed region can differ enormously.
- A complete power or ground plane is nearly full copper.
- A dense routing area has most of its copper etched away.
- A region with many component keepouts but little routing may end up as large blank areas.
These regions behave differently as the panel cools. Full-copper areas restrain the resin; blank areas do not. The result is a local stress gradient within one plane, and what it produces is not a clean overall bow but local ripple and twist. That class of deformation is usually the harder one, because it cannot be corrected by flattening the board as a whole.
The design-side answer is copper balance fill: adding isolated copper features to large bare regions, typically as a grid or dot array, either unconnected or tied to ground per your design rules. The point is not thermal and not shielding. The point is to level out copper retention so the layer shrinks consistently.
This has to happen at design time. Once the board is released, the fab will not add copper to your blank areas for you.
3. Second kind of asymmetry: how layers pair across the centreline
More damaging than within-layer distribution is the pairing relationship between layers.
Stand the stackup table on end and take the mid-thickness plane as the axis of symmetry. Ideally, two layers equidistant from that centre have the same copper weight, comparable copper retention, and equal dielectric thickness on either side. That is a symmetric stackup, and its shrinkage moments cancel naturally.
Symmetry typically breaks in a few ways:
1. The layer order itself is asymmetric. A 6-layer board that places both internal planes in the upper half leaves only signal layers below. The top half is copper-heavy and restrained, the bottom half shrinks freely, and the board bends one way by necessity.
2. Copper weight is asymmetric. Mixing copper weights across inner layers is legitimate — the copper weight range published on the SKPCB capabilities page runs from 0.5oz to >12oz with separate tiers for inner and outer layers — but if the heavy layers appear on one side only, the pairing is broken. The layer-order tradeoffs for mixed-weight builds are covered in heavy copper multilayer mixed-weight stackup.
3. Dielectric thickness is asymmetric. Swapping one side's prepreg for a thinner spec to hit an impedance target or an overall thickness target leaves unequal resin volume on the two sides. The resin-rich side shrinks more.
4. Outer layer asymmetry is the easiest one to overlook. A densely populated top side over a nearly bare bottom side is normal in many designs. The two outer layers can differ wildly in copper retention, and they sit farthest from the neutral axis, which gives them the longest lever arm — the same stress differential produces far more bending on an outer layer than on one near the centre.
The first three belong to stackup planning; the fourth belongs to layout. The multilayer stackup guide covers stackup construction in full. The point worth keeping here: symmetry is an item that has to be actively checked, not a default state that holds by itself.
4. Which asymmetries are already locked in at design time
Laying the two categories side by side, a line can be drawn.
Locked in — process cannot undo these:
- Asymmetric layer order, with internal planes concentrated on one side. This is structural; lamination parameters cannot reverse the direction of a moment.
- Severely unbalanced outer layer copper retention with no room to fill (for instance, a bottom side with genuinely no space for added copper).
- Broken copper weight pairing, with heavy copper on one side only.
- Unequal resin volume between the two sides, created to hit an overall thickness target.
Once any of these enters production, what remains is controlling the magnitude of warpage, not removing its cause.
Still open to process influence:
- Lamination ramp rate, the timing of pressure application, and hold time, all of which affect whether resin flow and therefore shrinkage is uniform. The specific parameters sit inside the production process window, are not published, and need to be set per stackup through engineering review.
- Panelization layout and orientation. Copper distribution across the full production panel has its own symmetry problem, and panelization is adjustable.
- Post-lamination stabilization before profiling. This releases and fixes part of the deformation that already formed — mitigation, not prevention.
- Support and handling through profiling and downstream operations, to avoid adding mechanical deformation to a board that already carries stress.
The reason for separating the two lists: review time should be spent on the first one. Every item in the first list is free — changing the design adds no manufacturing cost. Every item in the second carries a process cost and has a ceiling on what it can achieve.
5. Structures that make symmetry harder to achieve
Several situations tighten the constraint:
- High layer counts. More layers means more pairings that can go wrong. The SKPCB multilayer product page states a 4-64 layer range; the capabilities page states 2-64, with standard production to 40 layers and up to 64 for the most complex builds (product page FAQ). At the high end the stackup table has to be checked pair by pair, not just by total copper.
- Thin boards. Lower thickness means lower bending stiffness, so the same internal stress produces more deformation. The product page gives a 0.4-6.0mm thickness range and the tolerance page gives 0.2-6.0mm overall. Boards at the thin end are more sensitive to copper balance.
- Large panel sizes. Deformation scales with dimension, so the same curvature shows up as a larger absolute number on a bigger board.
- Mixed-material stackups. Different material systems have different shrinkage behaviour and Tg, so symmetry has to be assessed by material as well as by geometry. Available material systems are listed on the materials page.
- Impedance constraints. Impedance control locks dielectric thicknesses, which removes the freedom to use dielectric thickness for balancing. The multilayer product page lists ±5% impedance tolerance (±10% standard), and those builds have less stackup latitude.
6. Five things to do at design time
- Make symmetry an explicit check item. Once the stackup table is done, walk it pair by pair against the centre plane: same copper weight, same dielectric thickness, comparable copper retention. Any pair that fails needs a stated reason rather than passing by default.
- Add copper balance fill to every large bare region, inner and outer layers alike. Define the fill pattern, its clearance to routing, and whether it ties to a net in your design rules, and note it on the drawing.
- Balance the two outer layers. When the bottom side is largely empty, either fill it or move some plane copper down. This item pays more than inner-layer fill because the outer layers have the longest lever arm.
- Do not thin one side's dielectric to hit an overall thickness target. Adjust both sides symmetrically. When impedance and overall thickness conflict, raise the conflict for engineering review instead of sacrificing one side.
- State the flatness requirement on the drawing. Warpage is a specifiable acceptance item, but only if it appears on the drawing. Leaving it off means accepting the general standard's judgement criteria, which may not match your assembly method. The allowable value has to be confirmed by engineering review against board type, thickness and assembly requirements — SKPCB does not publish a single warpage figure, so this is confirmed per project. The full drawing release set is in the multilayer stackup drawing release checklist.
7. What the release side actually verifies
Beyond design and process there is a third layer: acceptance criteria.
The framework published on the SKPCB quality and capabilities pages is IPC-A-600 Class 2/3 acceptance and 100% full coverage electrical test, with a defect rate figure of <0.1%. These answer different questions:
- IPC-A-600 Class 2/3 is the visual and structural acceptance framework. Flatness falls inside its scope, judged per the selected Class and the drawing. Whether you want Class 2 or Class 3 should be stated at order placement, because the criteria differ.
- 100% electrical test verifies electrical continuity and has no direct relationship to warpage. This is worth stating plainly: a board that is out of spec on flatness can pass electrical test completely. Electrical test is not a safety net for flatness.
On the process side, the flow published on the capabilities page is 01 Cutting / 02 Inner Layer / 03 Lamination / 04 Drilling / 05 Plating / 06 Outer Layer / 07 Solder Mask / 08 Surface Finish / 09 Profiling / 10 Testing. The causes of warpage concentrate in 02-03, inner layer artwork and lamination, but the moment it becomes visible can be any thermal step after 04, or not until assembly. That is exactly why it has to be prevented on the design side rather than caught at the end of the line.
To have warpage risk assessed against a specific stackup, submit the stackup table, copper distribution and assembly method together through online quote, and engineering review will return actionable symmetry adjustments and a flatness specification.
FAQ
Does copper balance fill affect impedance or signal integrity?
Yes, which is why fill is not added blindly. Isolated copper features need adequate clearance to signal traces, and regions near sensitive routing — impedance-controlled lines and differential pairs especially — need to be evaluated. The working approach is to define fill as part of the design rule set rather than patching it in by hand at the end. On impedance-controlled boards, fill strategy should be confirmed alongside the impedance calculation.
If only the outer layers are asymmetric and all inner layers pair correctly, how much does it matter?
Potentially more than expected. The outer layers sit farthest from the mid-thickness plane, giving them the longest lever arm, so the same shrinkage differential produces the largest bending moment there. A densely populated top over a largely empty bottom is a very common design and a very common source of warpage. Where the bottom side has space, copper balance fill should be the first move.
Thin boards warp more easily, so does adding thickness solve it?
Added thickness raises bending stiffness, so the same internal stress produces less deformation. That lowers sensitivity rather than removing the cause. The stress is still inside the laminate, held down by a stiffer structure, and it can still release under later thermal shock. Overall thickness is also usually locked by assembly space and impedance, so it is not a free variable. The correct order is to fix symmetry first, then discuss thickness.
Can lamination parameters rescue a design that is already asymmetric?
They can reduce the magnitude, not change the direction or the cause. The lamination program affects whether resin flow and shrinkage are uniform, but a structural moment imbalance — asymmetric layer order, heavy copper on one side — is outside what lamination parameters reach. The applicable process window has to be set per stackup by engineering review.
Electrical test passed 100%. Does that mean the board has no warpage problem?
No. The 100% full coverage electrical test SKPCB publishes verifies electrical continuity; flatness is a separate criterion. Warpage is judged against the selected IPC-A-600 Class and the flatness requirement stated on the drawing. If the drawing states no flatness requirement, only the general standard's criteria apply.
How should warpage be written on the drawing?
At minimum: the agreed measurement method, the applicable area, and the corresponding IPC-A-600 acceptance Class. The allowable value needs engineering review against thickness, panel dimension and your assembly method — reflow, press-fit and screw-mounted assemblies impose very different constraints. SKPCB does not publish a single warpage figure, so this is confirmed per project and no default value should be assumed.