When a rush order gets rescheduled, capacity is usually not the reason. The board contains one feature that no amount of scheduling priority can move. Engineers often treat lead time as a continuous variable you buy down with money. It behaves like a staircase: certain design features move an order to an entirely different tier rather than making it one or two days slower.
Knowing where those steps sit gives you two things. You can tell which tier your board belongs to before you submit it, without waiting for a scheduling reply. And you learn which operations are never dropped under deadline pressure — because dropping them hands the risk straight to your assembly line.
Everything below follows the published figures on the SKPCB quick turn manufacturing page and capabilities page. Those figures are page-published values, not commitments for any specific board; the tier for a given project is confirmed by engineering and scheduling.
1. What a rush order actually compresses
Break "fast" apart first. A bare board runs the full sequence from cutting through inner layer, lamination, drilling, plating, outer layer, solder mask, surface finish, profiling and testing — the ten-step process flow published on /capabilities/. Quick turn removes none of these steps. It compresses three things:
Queue time. Standard orders wait in front of each machine for a batch. A rush order jumps to the front. This is the single largest source of quick-turn speed and the only part that compresses with essentially no cost.
Batch consolidation waiting. Standard production waits to gather boards of the same material and parameters to share setup cost. Rush orders do not wait for that; they run their own setup.
Logistics. /capabilities/ publishes international express options as DHL Express (2–4 days), FedEx (2–5 days), UPS (3–5 days), TNT (3–6 days) and EMS (5–10 days), with domestic China handled by SF Express / JD Logistics / Deppon, next-day within Guangdong and 2–3 days nationwide. Choosing a faster carrier buys transit days and touches no process step.
Beyond those three, the process itself has physical floors. Plating must deposit specified thickness. Lamination must complete its vacuum and thermal cycle. Surface finish must complete its chemistry. Solder mask must cure. None of these shorten because the order is flagged rush. So the lower bound on a quick-turn lead time is not zero. It sits at "required process time plus required inspection time".
2. How to read the published quick turn tiers
/quick-turn-pcb/ publishes typical quick-turn lead times by layer count:
| Layer count | Published typical quick-turn lead time |
|---|---|
| 1–2 layers | 24 hours |
| 4 layers | 48 hours |
| 6–8 layers | 72–96 hours |
| 10+ layers | 5–7 days |
The same page states that lead times vary with complexity, surface finish and order size, and that an exact schedule requires contact.
/capabilities/ gives lead times along a different axis: Rush Prototype 24–48h, Standard Prototype 3–5 days, Standard Production 5–7 days, Complex Boards 10–15 days.
Read both together. The layer table tells you where the baseline tier sits. The Complex Boards 10–15 day figure tells you where you land after falling out of quick-turn range. What decides between them is the feature list in the next section. A six-layer board defaults to 72–96 hours — but if it also demands Any Layer construction, 12oz inner copper and ±5% impedance, it is no longer "a six-layer board". It is a complex board.
One inference gets missed here: lead time does not grow linearly with layer count. 1–2 to 4 layers is 24→48 hours. Four to 6–8 layers is 48→72–96 hours. Ten and above jumps to 5–7 days. The jumps land where lamination cycles and drilling complexity change, not where the layer counter increments. For what changes between layer counts, see the 4/6/8 layer comparison.
3. Features that push an order out of quick-turn tiers
Every item below comes from the three-tier specification table on /capabilities/ (Standard / Advanced / R&D). Designs that fit inside Standard generally schedule against the layer table. Features requiring Advanced or R&D almost always reschedule as complex boards.
HDI depth and Any Layer. HDI 1+N+1 through 5+N+5 are all marked available across the three tiers, but Any Layer is offered only in Advanced and R&D — Standard shows "—". The reason is structural: more HDI levels mean more laser-drill, plating and lamination cycles, and each cycle is serial physical time. Any Layer pushes that cycle to every layer. These boards are not "a bit slower"; the number of process rounds itself increases. For HDI design inputs, see the HDI PCB page.
Copper above 3oz. Maximum inner and outer copper across the three tiers is 3oz / 12oz / >12oz. Anything above 3oz leaves Standard. Heavy copper drives etch time, line-width compensation and solder mask fill difficulty — all process time, not queue time. See copper thickness options and design rules and the heavy copper PCB page.
Board thickness at either end of the window. The overall window is 0.2–6.0 mm, but minimum board thickness with solder mask across the tiers is 0.6 / 0.40 / 0.20 mm, and maximum board thickness is 4 / 6 / 6 mm. Thinner than 0.6 mm or thicker than 4 mm requires Advanced or above. Thin panels need extra handling and anti-warp measures; thick panels take longer in lamination and drilling.
Line and space below 3 mil. Minimum inner and outer line/space across the tiers is 4/4 mil, 3/3 mil, 2/2 mil. Fine lines demand tighter exposure and etch control, typically LDI rather than conventional exposure, and they compress rework headroom to near zero — and rework is exactly what a rush order cannot absorb.
Mechanical holes below 0.2 mm, or laser drilling. Minimum mechanical hole across the tiers is 0.2 / 0.15 / 0.15 mm; minimum laser hole is 0.1 / 0.075 / 0.075 mm. Small holes mean slower drill speeds, more frequent tool changes and higher aspect-ratio risk (maximum PTH aspect ratio is 10:1 across all three tiers). For hole wall acceptance, see drilling hole quality inspection.
±5% impedance tolerance. /capabilities/ publishes impedance control at ±5%, with ±10% as standard. Accepting ±5% means building impedance coupons and adjusting line-width compensation against measured results, sometimes with a stack-up confirmation build. A confirmation build is a full manufacturing cycle, which no quick-turn tier contains. See impedance control tolerance classes.
Rigid-flex and embedded components. Rigid-Flex is marked available across all three tiers, but Embedded Components appear only in Advanced and R&D. Rigid-flex has a longer process chain, with different material preparation and lamination methods. See the rigid-flex PCB page.
Special surface finishes. /quick-turn-pcb/ states explicitly that lead time varies with surface finish. The /capabilities/ comparison table lists ENIG, ENEPIG and Hard Gold at Medium, High and High cost against Low for HASL and LF-HASL. Electroless and electrolytic gold processes take longer in the chemistry than HASL, and Hard Gold often adds selective masking steps. If you need speed and not a specific solderability property, surface finish is one of the few variables you can genuinely trade for lead time — after confirming it does not break your assembly process. See the surface finish page.
Board size outside the tier. Maximum board size across the tiers is 600×570 / 610×1100 / 1250×570 mm; minimum board size is 50×50 / 30×30 / 5×5 mm. Both oversized and very small boards need dedicated panelization and tooling plans.
A practical method: check every parameter of your design against the three-tier table and find the highest tier you touch. If any single requirement lands in the Advanced or R&D column, stop estimating from the layer table. Treat it as a complex board and ask engineering to evaluate.
4. Operations that are never cut, at any lead time
This is the part that matters most. Section 3 covered what makes you slower. This covers what will not be dropped even if you offer to accept the risk.
100% electrical test. /capabilities/ publishes 100% full-coverage electrical test as its quality control standard. It is not optional. An open or short found after assembly costs the board plus every component and every minute of labour on it. Flying probe testing (ATG flying probe in the published equipment list) is actually well suited to rush work because it needs no test fixture — so trading testing for lead time does not even pay off economically.
AOI. Inner-layer imaging is sealed inside the board permanently once lamination completes. AOI before lamination is the last opportunity to catch an inner-layer defect. Skipping it means carrying a possibly scrap board through the remaining seven operations.
IPC-A-600 acceptance. /capabilities/ publishes acceptance to IPC-A-600 Class 2/3. Acceptance class is a contractual property, not a scheduling one — it does not downgrade because an order is rushed. If your project calls for Class 3, the rush build is judged to Class 3.
Required process time in lamination and plating. Vacuum lamination (Burkle vacuum lamination press in the published equipment list) must complete evacuation, ramp, dwell and cool-down. Vertical continuous plating (Atotech VCP) must deposit to specification. These are chemical and thermal processes with no accelerator switch.
X-ray target drilling. After lamination, a multilayer board needs X-ray (Pluritec X-ray drilling target machine) to locate inner-layer datums before drilling. Skipping it means abandoning layer-to-layer registration. For the full treatment of registration and scaling, see multilayer lamination registration control.
There is another way to see this. Rework on a rush order costs far more than on a standard order, because it has no buffer. Rework on a standard build may mean two days late; rework on a 24-hour build means the lead time is simply gone. Inspection is not a tax on quick turn. It is how the quick turn holds.
5. What to have ready when you place a rush order
Quick-turn lead time starts when the data package is complete, not when you send the email. These gaps stop the clock before it starts:
Complete Gerber or ODB++, with drill files and a layer order note. Ambiguous layer order triggers an engineering query, and one query round can consume half a day — out of a 24-hour total.
Stated board thickness and tolerance form. A nominal thickness alone is not a complete specification; the tolerance form and what the measurement includes both need to be stated. See the published figures on the manufacturing tolerance page.
Stated surface finish and acceptance class. Both directly determine the tier. Leaving either blank means waiting for confirmation.
Impedance requirements with target value, tolerance and reference plane. "Impedance controlled" alone does not let engineering build a stack-up.
Material requirements at least to category level. You do not need to name a grade, but say whether it is standard FR-4, high-Tg, halogen-free or high-frequency. Material availability is one of the few genuine external variables that can stall a rush order. See the materials library.
Panelization and delivery format. Single boards or arrays, process edges or not, V-cut or routed — each affects how profiling is scheduled.
The principle in one line: a rush order cannot contain any blank that requires going back for confirmation. Every blank is a round trip, and round trips are billed in hours at this tier.
Once the files are ready, submit through the quote page and note both your target date and whether you accept surface finish alternatives. That last point is often where engineering can win a tier back for you.
6. When not to use quick turn
Three situations where rush money goes to the wrong place:
The design is not frozen. If you expect another revision, the first rushed board has limited value. Validate with standard prototyping and save the urgency for later.
First build of a complex board. A board with Any Layer, very heavy copper or ±5% impedance needs engineering review time on its first run, not scheduling priority. Skipping review usually buys a rework cycle.
Assembly follows immediately. If the bare board goes straight to SMT, rushing the bare board only moves the bottleneck one step downstream. Schedule the bare board and assembly together in that case.
FAQ
Can a 4-layer board really ship in 48 hours?
/quick-turn-pcb/ publishes 48 hours as the typical quick-turn lead time for 4 layers, and notes on the same page that lead times vary with complexity, surface finish and order size. A conventional 4-layer board with Standard-tier parameters and a complete data package corresponds to that tier. If it also requires fine lines, heavy copper or ±5% impedance, the tier changes. Confirm the specific project with engineering and scheduling.
Does a rush order lower acceptance standards?
No. /capabilities/ publishes acceptance to IPC-A-600 Class 2/3 with 100% electrical test, and that quality standard is independent of lead time. Quick turn changes queueing and batching strategy, not the judgement criteria.
Which single feature most often breaks a quick turn?
By the three-tier table, Any Layer and Embedded Components trigger a tier jump most directly — both are marked as not offered in Standard. Next are copper above 3oz, board thickness with solder mask below 0.6 mm or above 4 mm, and line/space below 3 mil.
Can changing the surface finish buy a faster lead time?
/quick-turn-pcb/ states that lead time varies with surface finish, and electroless or electrolytic gold chemistry takes longer than HASL. So where your assembly process allows it, surface finish is a legitimate lead-time variable. Confirm the assembly impact first: the /capabilities/ comparison table marks HASL and LF-HASL as unsuitable for both fine-pitch SMT and BGA/μBGA.
Why do 10+ layers jump straight to 5–7 days?
High layer counts increase lamination rounds, drilling time and layer-to-layer registration demands, and lamination is followed by X-ray target location. These are serial process times that queue priority cannot shorten. /quick-turn-pcb/ publishes 5–7 days for 10+ layers.
Can part of the order be rushed, for example a few pieces first?
That is a scheduling arrangement to confirm with engineering and production. Note that split delivery means the same order runs across different production batches. If your project needs batch consistency — for example impedance or thickness matched within one batch — raise it at order placement.
My board was classified as complex. Any way to speed it up?
Look back at the design for high-tier requirements that are not strictly necessary: whether impedance truly needs ±5% instead of the ±10% standard, whether inner copper can drop from 4oz to 3oz, whether 1+N+1 can replace Any Layer. Each Advanced-tier requirement removed may pull the order back into layer-table scheduling. These trade-offs need engineering evaluation, so state your negotiable items directly when you request a quote.