Thick Copper PCB Manufacturing Limits: What Trace Width, Spacing and Solder Mask Give Up

Why the Capability Table Gets Misread

Capability tables invite a combination that does not exist.

The copper weight row reads up to 12oz. The minimum trace width row reads down to 2mil/2mil. So a design arrives with 10oz copper, 6mil traces, 6mil spacing, and a note requiring solder mask to fully encapsulate every trace edge. Engineering review sends it back, and the designer's first response is usually "your capability table says you can do this."

The table is not wrong. The reading is. It is a table of single-parameter limits, not a table of guaranteed combinations. Every row states what that one parameter can reach when the others sit in a friendly state. Rows do not multiply across.

Thick copper is where this misreading costs the most, because copper weight is not an isolated parameter. It draws down margin in three directions at once: etching takes from trace width and spacing, solder mask takes from coverage capability, lamination takes from resin fill volume. Raise the copper weight one tier and all three degrade together, and not linearly.

This article answers that combination question. Why each margin gets consumed, in what order to give it up, which limits are genuinely physical versus merely unstated, and how to write the drawing so the factory follows your intent instead of its defaults.

> How this differs from the product page: /en/products/heavy-copper-pcb/ answers whether this fab does heavy copper, across what range, and for which applications — a capability-ownership question. This article does not repeat that. It answers what you have to actively give up at a given copper weight and what you must add to the drawing — a design-input question. Use them together: confirm the range on the product page, then use this to decide how your design has to change.

1. Read the Capability Table Correctly First

The detailed specification table on SKPCB /en/capabilities/ gives values across three tiers: Standard / Advanced / R&D. The rows relevant to thick copper read as follows:

The point: values in the same column do not constitute a simultaneously achievable configuration. The 2mil/2mil cell corresponds to thin copper with high-resolution imaging and fine etch control. The >12oz cell corresponds to a heavy-copper etch and compensation flow. Pull the two cells together and the physics does not hold — the next section explains why.

This is not a quirk of SKPCB's wording. Nearly every PCB capability table is a single-parameter limit table. Thick copper simply has the sharpest combination conflict, so it has to be stated plainly here.

2. First Margin Lost: Etching Takes Trace Width and Spacing

Undercut Scales with Thickness, Not Width

Subtractive etching works by having resist protect the copper you want to keep while etchant attacks the exposed areas. The problem is that etchant does not only move downward — it attacks sideways at the same time. Thicker copper needs longer etch time, so more material is removed from the sides.

The conductor cross-section turns from an ideal rectangle into a trapezoid: narrow at the top and wider at the base, or the reverse depending on process detail. The amount of distortion broadly increases with copper weight. Two things then happen at once:

1. Trace width no longer equals what you drew. To land the finished top width on your design value, the artwork must be widened in advance. That is etch compensation.
2. Spacing is consumed by the compensation. Every trace in the artwork grew wider, so the gap between adjacent traces narrowed by the same mechanism. The 6mil gap you drew may be considerably smaller in the artwork.

So on thick copper, trace width and spacing are two line items in the same budget. You cannot relax width while preserving spacing, nor tighten spacing while preserving width.

What Follows From This

• The higher the copper weight, the larger the achievable minimum line/space. The 2mil/2mil tier is not available under thick copper conditions.
• Etch compensation belongs on the manufacturing side. Do not pre-compensate in your own artwork. If you already have and you do not declare it on the drawing, the factory will compensate a second time and the trace width will run out of tolerance.
• Trace width tolerance has to be read proportionally. /en/tolerance/ states trace width at ±20%, with another statement of ±10% or ±0.005″, whichever is greater. The percentage basis is generous for wide conductors while the absolute basis governs narrow ones. On thick copper, what you should actually be policing is cross-sectional area, not width.

> The full compensation and trace-width tolerance logic, and why cross-sectional area rather than width is the acceptance focus, is covered in heavy copper etch compensation and trace width tolerance. This article only uses its conclusion.

Controllable Variables

• Copper weight tier selection. Do not default to the maximum. Calculate the cross-sectional area you need, then work back to the lowest acceptable copper weight. One tier down returns both trace width and spacing margin.
• Mixed-weight stackup. If only a few layers carry high current, the whole board does not need thick copper. Route high-current layers in heavy copper and signal layers at conventional weight, and fine features return to a normal process window. Stackup and lamination constraints for that route are in heavy copper multilayer mixed-weight stackup.
• Local width relief. Widen only the conductors on the current path rather than raising the board-wide minimum trace width.

3. Second Margin Lost: Solder Mask Takes Coverage Capability

Thick Copper Is a Step on the Board Surface

At conventional copper weight, the height difference a trace creates is small enough that solder mask flows over it without difficulty. Thick copper is different: the trace becomes a genuine raised structure, and the mask has to cover the top face, run down the sidewall, and continue onto the substrate.

Screen-printed solder mask is applied by a squeegee pushing paste through a stencil. At a step, paste is scraped thin on the top face, accumulates unevenly on the sidewall, and tends to leave a weak band at the base of the step. Those are the three characteristic risk locations on thick copper:

• Thin coverage on the trace top face — reduced insulation and environmental margin.
• Uneven sidewall coverage — thick copper sidewalls are already an imperfectly vertical slope, making consistent paste adhesion difficult.
• Weakness or micro-voids at the step base — the starting point for later delamination, plating bleed and electrical failure.

Higher copper weight means a taller step and all three risks rise together. This is a physical constraint, not a question of process competence. Better process control improves consistency; it does not remove the step.

What Follows From This

• Do not specify "solder mask fully encapsulates every trace edge" on thick copper. For sufficiently heavy copper this requirement is not reliably achievable with screen printing. Either accept coverage variation on top faces and sidewalls, or change the structure (below).
• Solder mask dams are harder on thick copper. A dam between adjacent heavy conductors must bridge two steps while being squeezed by the spacing budget. Narrow dams break readily under thick copper conditions.
• Surface finish access is affected. Steps and uneven mask edges change how downstream chemistry flows and rinses, so surface finish uniformity is dragged along.

> The specific coverage limits and acceptance basis for solder mask and surface finish on thick copper are in heavy copper solder mask and surface finish coverage.

Controllable Variables

• Open up spacing to give dams room, or explicitly state that certain regions need no dam at all.
• Design exposed copper as solid areas rather than dense fine traces. A solid pour has one step at its perimeter; dense fine traces are a continuous array of steps, which is far harder.
• Identify which edges are functional. If one conductor's edge coverage matters for insulation, call it out separately on the drawing and accept conventional criteria elsewhere. A blanket "full solder mask coverage board-wide" note raises every location to the highest requirement, which leaves the factory no option but to reject the whole package.

4. Third Margin Lost: Lamination Takes Resin Fill Volume

Thick copper inner layers present a severely uneven surface before pressing. Prepreg must flow during lamination to fill every gap between conductors while maintaining dielectric thickness. Thicker copper means more volume to fill, which raises the demand on prepreg resin content and flow.

Incomplete fill produces voids and delamination. Uneven fill produces inconsistent dielectric thickness and board warpage. Vacuum lamination — the Burkle vacuum lamination press listed on /en/capabilities/ — exists to reduce exactly this class of risk, but what it improves is air evacuation and fill consistency. It cannot create resin volume that is not there.

Three knock-on design constraints follow:

• Board thickness goes up. To secure fill and interlayer insulation, thick copper stackups typically need more or thicker prepreg. The board thickness ceiling on /en/capabilities/ is 6.0mm, and heavy copper multilayers approach it considerably faster than conventional boards.
• Uneven copper distribution amplifies warpage. Thick copper is stiff in itself, so once layer-to-layer copper area is asymmetric, stresses through lamination and later thermal processes are harder to balance. Balancing practice is in multilayer copper balance and warpage control.
• The drilling and aspect ratio window tightens. Thicker board at unchanged hole diameter degrades aspect ratio. The maximum aspect ratio on /en/capabilities/ is 10:1, with minimum mechanical hole at 0.2mm standard and 0.15mm advanced. On heavy copper multilayers these two numbers must be calculated together, never one in isolation.

5. The Order of Concession: What to Give Up First

When requirements exceed the process window, engineering review will ask for concessions. There is a low-to-high cost order, and following it minimises rework:

1. Reduce copper weight first. Work back from the cross-sectional area you actually need rather than taking the capability ceiling. This single step releases trace width, spacing, solder mask and lamination margin simultaneously — the only change that buys four things at once.
2. Then change the stackup strategy. Put only the high-current layers in heavy copper and return the rest to conventional weight. The constraint is confined to a few layers.
3. Then open up spacing. Relaxing spacing rescues both solder mask dams and etch compensation, a better return than relaxing width alone.
4. Then widen traces. Wider conductors solve current carrying and etching, but do nothing about the solder mask step.
5. Then downgrade the solder mask requirement. Convert "full coverage board-wide" into zoned requirements with functional edges called out separately. Lowest cost of all, but it must be written out explicitly or the factory can only judge against the highest requirement.
6. Only then touch board thickness and layer count. This affects cost, the drilling window and whole-board mechanical behaviour. Last resort.

Note the contrast between step 1 and step 6: reducing copper weight has almost no side effects, while adding thickness degrades aspect ratio as a consequence. Invert the order and the problem simply relocates to the drilling stage.

6. Six Items That Must Be Explicit on the Drawing

Half the time, thick copper packages come back not because capability is lacking but because the constraint was never written down, so the factory applied its defaults. These six belong on the drawing or in the stackup document:

1. Per-layer copper weight. State finished copper weight layer by layer, and say whether the figure is finished or base copper. Mixed-weight stackups especially need layer-by-layer notation.
2. Etch compensation ownership. State either "Gerber is design dimension, compensation applied by manufacturing" or "Gerber already includes compensation." Omit this line and double compensation happens.
3. Trace width acceptance basis. State whether acceptance is on top width, base width or cross-sectional area, and which tolerance statement applies (the ±20% basis on /en/tolerance/ or the ±10% / ±0.005″ whichever-greater basis). For current-carrying purposes, cross-sectional area is the sound choice.
4. Critical spacing and solder mask dam callouts. Mark the gaps that cannot be opened up, and equally mark the regions where no dam is required. Both marked, the factory knows where it has room to work.
5. Zoned solder mask requirements. Separate "functional insulation edges" from "conventional coverage areas" and give each its own acceptance basis. Do not apply one blanket maximum requirement.
6. Priority between board thickness and aspect ratio. State whether board thickness is a hard constraint or may float with the stackup. If thickness is fixed while the heavy copper stackup needs more resin, specify which takes precedence: dielectric thickness or overall thickness.

Get these six right and engineering review usually clears in one round. Leave them vague and the clarification loop typically costs more time than changing the design would have.

7. Downstream Consequences: Drilling, Test and Routing

Thick copper does not stop at those three margins. Engineering review also looks at:

• Drilling. Added board thickness compresses the aspect ratio window (10:1 ceiling), and thick copper layers change drilling load and chip evacuation behaviour. On the equipment side /en/capabilities/ lists a Hitachi high-speed drilling machine; hole quality inspection basis is in PCB drilling hole quality inspection.
• Electrical test. The low impedance of thick copper makes small defects harder to expose in conventional testing, so the test method has to be agreed up front. The applicability boundaries of the two mainstream approaches are in flying probe versus test fixture.
• Routing. Milling load on thick copper exceeds conventional boards, so edge quality and tolerance need confirming together. Maximum board size 1250×570mm (R&D tier) is the hard boundary for outline design.

Related Links

• Heavy copper etch compensation and trace width tolerance
• Heavy copper solder mask and surface finish coverage
• PCB copper thickness options and design rules
• Heavy copper multilayer mixed-weight stackup
• Multilayer copper balance and warpage control
• Thick copper PCB product page
• Manufacturing capabilities overview

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FAQ

Q: The table lists max outer copper at 12oz and min line/space at 2mil/2mil. Can I have 12oz with 2mil traces?

A: No. It is a single-parameter limit table where each row states that parameter's boundary when the others are friendly; rows do not combine across. 2mil/2mil corresponds to thin copper conditions and 12oz to a heavy-copper etch flow. Achievable trace width grows with copper weight, and the specific combination has to be confirmed from project data.

Q: What basis should thick copper trace width be accepted on?

A: Cross-sectional area rather than top width. /en/tolerance/ states trace width at ±20%, with a further ±10% or ±0.005″ whichever-greater basis. Etch undercut makes the thick copper cross-section trapezoidal, so measuring top width alone understates actual current-carrying capability. State the chosen basis on the drawing.

Q: I already applied etch compensation in my Gerber. Do I need to tell the factory?

A: Yes, and on the drawing rather than only by email. Manufacturing assumes Gerber is the design dimension and compensates on its own. Your compensation plus theirs puts trace width out of tolerance.

Q: Can I require solder mask to fully encapsulate every trace edge on thick copper?

A: Not advisable for sufficiently heavy copper. Thick conductors form a step on the board surface, and thin coverage on top faces, uneven sidewalls and weakness at the step base are physical outcomes of screen printing. The correct approach is separating functional insulation edges from conventional coverage areas with distinct acceptance criteria.

Q: Thick copper on every layer, or only some?

A: Only the layers carrying high current need it. A mixed-weight stackup confines the fine-feature and solder mask constraints to a few layers, making it the highest-value adjustment in heavy copper design. Stackup and lamination implications need confirming in parallel.

Q: Does thick copper make the board thicker?

A: Usually yes. Heavy copper inner layers need more resin to fill the gaps between conductors, so the stackup typically needs more or thicker prepreg. The thickness ceiling is 6.0mm, heavy copper multilayers approach it faster than conventional boards, and that in turn compresses the aspect ratio window (10:1 ceiling).